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參數(shù)資料
| 型號(hào)： | DM74LS670MX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | Register File |
| 中文描述： | 4 X 4 STANDARD SRAM, 55 ns, PDSO16 |
| 封裝： | 0.150 INCH, MS-012, SOIC-16 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 65K |
| 代理商： | DM74LS670MX |
2000 Fairchild Semiconductor Corporation
DS006436
www.fairchildsemi.com
August 1986
Revised March 2000
D
DM74LS670
3-STATE 4-by-4 Register File
General Description
These register files are organized as 4 words of 4 bits
each, and separate on-chip decoding is provided for
addressing the four word locations to either write-in or
retrieve data. This permits writing into one location, and
reading from another word location, simultaneously.
Four data inputs are available to supply the word to be
stored. Location of the word is determined by the write
select inputs A and B, in conjunction with a write-enable
signal. Data applied at the inputs should be in its true form.
That is, if a high level signal is desired from the output, a
high level is applied at the data input for that particular bit
location. The latch inputs are arranged so that new data
will be accepted only if both internal address gate inputs
are HIGH. When this condition exists, data at the D input is
transferred to the latch output. When the write-enable
input, G
W
, is HIGH, the data inputs are inhibited and their
levels can cause no change in the information stored in the
internal latches. When the read-enable input, G
R
, is HIGH,
the data outputs are inhibited and go into the high imped-
ance state.
The individual address lines permit direct acquisition of
data stored in any four of the latches. Four individual
decoding gates are used to complete the address for read-
ing a word. When the read address is made in conjunction
with the read-enable signal, the word appears at the four
outputs.
This arrangement—data entry addressing separate from
data read addressing and individual sense line — elimi-
nates recovery times, permits simultaneous reading and
writing, and is limited in speed only by the write time (27 ns
typical) and the read time (24 ns typical). The register file
has a non-volatile readout in that data is not lost when
addressed.
All inputs (except read enable and write enable) are buff-
ered to lower the drive requirements to one normal Series
DM74LS load, and input clamping diodes minimize switch-
ing transients to simplify system design. High speed, dou-
ble ended AND-OR-INVERT gates are employed for the
read-address function and have high sink current, 3-STATE
outputs. Up to 128 of these outputs may be wire-AND con-
nected for increasing the capacity up to 512 words. Any
number of these registers may be paralleled to provide n-
bit word length.
Features
I
For use as:
Scratch pad memory
Buffer storage between processors
Bit storage in fast multiplication designs
I
Separate read/write addressing permits simultaneous
reading and writing
I
Organized as 4 words of 4 bits
I
Expandable to 512 words of n-bits
I
3-STATE versions of DM74LS170
I
Fast access times 20 ns typ
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number
DM74LS670M
DM74LS670N
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM74LS670M | 3-STATE 4-by-4 Register File |
| DM74LS670N | 3-STATE 4-by-4 Register File |
| DM74LS73A | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs(帶清零和互補(bǔ)輸出的雙負(fù)邊緣觸發(fā)的主-從J-K觸發(fā)器) |
| DM74LS73AM | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs |
| DM74LS73AN | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM74LS670N | 功能描述:寄存器 3-STATE 4-by-4 Reg RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| DM74LS73A WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| DM74LS73AM | 功能描述:觸發(fā)器 Dual J-K Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| DM74LS73AN | 功能描述:觸發(fā)器 Dual J-K Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| DM74LS74 WAF | 制造商:Texas Instruments 功能描述: |
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