參數(shù)資料
型號(hào): DM74LS75M
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Quad Latch
中文描述: LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDSO16
封裝: 0.150 INCH, MS-012, SOIC-16
文件頁(yè)數(shù): 1/5頁(yè)
文件大小: 49K
代理商: DM74LS75M
2000 Fairchild Semiconductor Corporation
DS006374
www.fairchildsemi.com
August 1986
Revised March 2000
D
DM74LS75
Quad Latch
General Description
These latches are ideally suited for use as temporary stor-
age for binary information between processing units and
input/output or indicator units. Information present at a data
(D) input is transferred to the Q output when the enable is
HIGH, and the Q output will follow the data input as long as
the enable remains HIGH. When the enable goes LOW, the
information (that was present at the data input at the time
the transition occurred) is retained at the Q output until the
enable is permitted to go HIGH.
These latches feature complementary Q and Q outputs
from a 4-bit latch, and are available in 16-pin packages.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
(Each Latch)
Function Table
(Each Latch)
H
=
HIGH Level
L
=
LOW Level
X
=
Don't Care
Q
0
=
The Level of Q Before the HIGH-to-LOW Transition of ENABLE
Connection Diagram
Order Number
DM74LS75M
DM74LS75N
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Outputs
D
L
H
X
Enable
H
H
L
Q
L
H
Q
0
Q
H
L
Q
0
相關(guān)PDF資料
PDF描述
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DM74LS83A 4-Bit Binary Adder with Fast Carry(帶快速進(jìn)位的4位二進(jìn)制加法器)
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DM74LS75N 功能描述:閉鎖 Quad Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
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