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參數(shù)資料
| 型號(hào)： | DM74S257N |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3-STATE Quad 1-of-2 Data Selector/Multiplexer |
| 中文描述： | S SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001, DIP-16 |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 47K |
| 代理商： | DM74S257N |
2000 Fairchild Semiconductor Corporation
DS006482
www.fairchildsemi.com
August 1986
Revised May 2000
D
DM74S257
3-STATE Quad 1-of-2 Data Selector/Multiplexer
General Description
These Schottky-clamped high-performance multiplexers
feature 3-STATE outputs that can interface directly with
data lines of bus-organized systems. With all but one of the
common outputs disabled (at a high impedance state), the
low impedance of the single enabled output will drive the
bus line to a HIGH or LOW logic level. To minimize the pos-
sibility that two outputs will attempt to take a common bus
to opposite logic levels, the output enable circuitry is
designed such that the output disable times are shorter
than the output enable times.
This 3-STATE output feature means that n-bit (paralleled)
data selectors with up to 258 sources can be implemented
for data buses. It also permits the use of standard TTL reg-
isters for data retention throughout the system.
Features
I
3-STATE versions S157, S158, with same pin-outs
I
Schottky-clamped for significant improvement in
A-C performance
I
Provides bus interface from multiple sources in high-per-
formance systems
I
Average propagation delay from data input
I
Typical power dissipation
4.8 ns
320 mW
Ordering Code:
Connection Diagram
Function Table
H
=
HIGH Level
L
=
LOW Level
X
=
Don’t Care
Z
=
High Impedance (OFF)
Order Number
DM74S257N
Package Number
N16E
Package Description
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Select
Output
Y
Output
Control
H
L
L
L
L
A
B
X
L
L
H
H
X
L
H
X
X
X
X
X
L
H
Z
L
H
L
H
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