參數(shù)資料
型號(hào): DM74S299N
廠(chǎng)商: FAIRCHILD SEMICONDUCTOR CORP
元件分類(lèi): 通用總線(xiàn)功能
英文描述: 3-STATE 8-Bit Universal Shift/Storage Register
中文描述: S SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP20
封裝: 0.300 INCH, PLASTIC, MS-001, DIP-20
文件頁(yè)數(shù): 4/5頁(yè)
文件大?。?/td> 58K
代理商: DM74S299N
www.fairchildsemi.com
4
D
Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Note 8:
T
A
=
25
°
C and V
CC
=
5V.
Note 9:
All typicals are at V
CC
=
5V, T
A
=
25
°
C.
Note 10:
Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics
at V
CC
=
5V and T
A
=
25
°
C (See Section 1 for Test Waveforms and Output Load)
Note 11:
C
L
=
5 pF.
Note 12:
R
L
=
1K
for delays measured to Q
A
and Q
H
.
Note 13:
For testing f
MAX
all outputs are loaded simultaneously.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 8)
V
I
V
OH
Input Clamp Voltage
HIGH Level
Output Voltage
V
CC
=
Min, I
I
=
18 mA
V
CC
=
Min, I
OH
=
Max
V
IL
=
Max, V
IH
=
Min
V
CC
=
Min, I
OL
=
Max
V
IH
=
Min, V
IL
=
Max
V
CC
=
Max, V
I
=
5.5V
V
CC
=
Max
V
I
=
2.7V
1.2
V
Q
A
thru Q
H
Q
A
, Q
H
2.4
2.7
3.2
3.4
V
V
OL
LOW Level
Output Voltage
Input Current @ Max Input Voltage
0.5
V
I
I
I
IH
1
mA
HIGH Level
Input Current
A thru H,
S0, S1
Any Other
100
μ
A
50
2
0.5
0.25
I
IL
LOW Level
Input Current
V
CC
=
Max
V
I
=
0.5V
Clock, Clear
S0, S1
Other
mA
I
OZH
Off-State Output Current with
HIGH Level Output Voltage
Applied (Q
A
thru Q
H
)
Off-State Output Current with
LOW Level Output Voltage
Applied (Q
A
thru Q
H
)
Short Circuit Output
Current (Q
A
thru Q
H
)
Short Circuit Output
V
CC
=
Max, V
O
=
2.4V
V
IH
=
Min, V
IL
=
Max
100
μ
A
I
OZL
V
CC
=
Max, V
O
=
0.5V
V
IH
=
Min, V
IL
=
Max
250
μ
A
I
OS
V
CC
=
Max
40
100
mA
(Note 10)
V
CC
=
Max
20
100
Current (Q
A
, Q
H
)
Supply Current
(Note 10)
I
CC
V
CC
=
Max
140
225
mA
R
L
=
280
(Note 12)
C
L
=
15 pF
Min
Max
50
Symbol
Parameter
From (Input)
C
L
=
50 pF
Min
40
Units
To (Output)
(Note 13)
Max
f
MAX
t
PLH
Maximum Clock Frequency
MHz
Propagation Delay Time
LOW-to-HIGH Level Output (Note 12)
Propagation Delay Time
Clock to Q
A
or Q
H
20
22
ns
t
PHL
Clock to Q
A
or Q
H
20
23
ns
HIGH-to-LOW Level Output (Note 12)
Propagation Delay Time
LOW-to-HIGH Level Output
t
PLH
Clock to Q
A
thru Q
H
21
ns
t
PHL
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
Clock to Q
A
thru Q
H
21
ns
t
PHL
Clear to Q
A
or Q
H
21
24
ns
HIGH-to-LOW Level Output (Note 12)
Propagation Delay Time
HIGH-to-LOW Level Output
t
PHL
Clear to Q
A
thru Q
H
24
ns
t
PZH
Output Enable Time to HIGH Level Output
G1, G2 to Q
A
thru Q
H
18
ns
t
PZL
Output Enable Time to LOW Level Output
G1, G2 to Q
A
thru Q
H
18
ns
t
PHZ
Output Disable Time to HIGH Level Output (Note 11) G1, G2 to Q
A
thru Q
H
12
ns
t
PLZ
Output Disable Time to LOW Level Output (Note 11)
G1, G2 to Q
A
thru Q
H
12
ns
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PDF描述
DM74S299 3-STATE 8-Bit Universal Shift/Storage Register(三態(tài)輸出的8位通用移位/存儲(chǔ)寄存器)
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