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參數(shù)資料
| 型號(hào)： | DM74S374WMX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Octal D-Type Flip-Flop |
| 中文描述： | S SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 封裝： | 0.300 INCH, MS-013, SOIC-20 |
| 文件頁(yè)數(shù)： | 4/7頁(yè) |
| 文件大?。?/td> | 72K |
| 代理商： | DM74S374WMX |
www.fairchildsemi.com
4
D
DM74S373 Switching Characteristics
at V
CC
=
5V and T
A
=
25
°
C
Note 8:
C
L
=
5 pF
DM74S374 Recommended Operating Conditions
Note 9:
C
L
=
15 pF, R
L
=
280
, T
A
=
25
°
C and V
CC
=
5V.
Note 10:
C
L
=
50 pF, R
L
=
280
, T
A
=
25
°
C and V
CC
=
5V.
Note 11:
The symbol (
↑
) indicates the rising edge of the clock pulse is used for reference.
Note 12:
T
A
=
25
°
C and V
CC
=
5V.
R
L
=
280
Symbol
Parameter
From (Input)
C
L
=
15 pF
Min
C
L
=
50 pF
Min
Units
To (Output)
Max
Max
t
PLH
Propagation Delay Time
Data to Any Q
12
14
ns
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
t
PHL
Data to Any Q
12
16
ns
t
PLH
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
Enable to Any Q
14
14
ns
t
PHL
Enable to Any Q
18
21
ns
HIGH-to-LOW Level Output
Enable Time to
HIGH Level Output
t
PZH
Output Control to Any Q
15
17
ns
t
PZL
Output Enable Time to
LOW Level Output
Output Disable Time to
Output Control to Any Q
18
23
ns
t
PHZ
Output Control to Any Q
9
ns
HIGH Level Output (Note 8)
Output Disable Time to
LOW Level Output (Note 8)
t
PLZ
Output Control to Any Q
12
ns
Symbol
Parameter
Min
4.75
Nom
5
Max
5.25
Units
V
V
V
V
CC
V
IH
V
IL
I
OH
I
OL
f
CLK
f
CLK
t
W
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
0.8
6.5
20
75
HIGH Level Output Current
LOW Level Output Current
Clock Frequency (Note 9)
mA
mA
MHz
0
Clock Frequency (Note 10)
Pulse Width
(Note 9)
0
6
75
MHz
Clock HIGH
Clock LOW
7.3
ns
Pulse Width
(Note 10)
Data Setup Time (Note 11)(Note 12)
Clock HIGH
Clock LOW
15
15
5
↑
2
↑
0
t
SU
t
H
T
A
ns
Data Hold Time (Note 11)(Note 12)
Free Air Operating Temperature
ns
°
C
70
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