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參數(shù)資料
| 型號(hào)： | DM74S74N |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs |
| 中文描述： | S SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001, DIP-14 |
| 文件頁數(shù)： | 3/5頁 |
| 文件大?。?/td> | 50K |
| 代理商： | DM74S74N |
3
www.fairchildsemi.com
D
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 5:
All typicals are at V
CC
=
5V, T
A
=
25
°
C.
Note 6:
Clear is tested with preset HIGH and preset is tested with clear HIGH.
Note 7:
Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 8:
With all outputs OPEN, I
CC
is measured with the Q and Q outputs HIGH in turn. At the time of measurement, the clock is grounded.
Switching Characteristics
at V
CC
=
5V and T
A
=
25
°
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 5)
V
I
V
OH
Input Clamp Voltage
HIGH Level
Output Voltage
V
CC
=
Min, I
I
=
18 mA
V
CC
=
Min, I
OH
=
Max
V
IL
=
Max, V
IH
=
Min
V
CC
=
Min, I
OL
=
Max
V
IH
=
Min, V
IL
=
Max
1.2
V
2.7
3.4
V
V
OL
LOW Level
Output Voltage
Input Current @ Max Input Voltage V
CC
=
Max, V
I
=
5.5V
HIGH Level
Input Current
0.5
V
I
I
I
IH
1
mA
V
CC
=
Max
V
I
=
2.7V
D
Clear
Preset
50
150
100
μ
A
Clock
D
Clear
100
2
6
4
4
100
50
I
IL
LOW Level
Input Current
V
CC
=
Max
V
I
=
0.5V
(Note 6)
mA
Preset
Clock
I
OS
I
CC
Short Circuit Output Current
V
CC
=
Max (Note 7)
V
CC
=
Max, (Note 8)
40
mA
Supply Current
30
mA
R
L
=
280
Symbol
Parameter
From (Input)
C
L
=
15 pF
Min
75
C
L
=
50 pF
Min
65
Units
To (Output)
Max
Max
f
MAX
t
PLH
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
MHz
Preset to Q
6
9
ns
t
PLH
Propagation Delay Time
LOW-to-HIGH Level Output
Clear to Q
6
9
ns
t
PHL
Propagation Delay Time
HIGH-to-LOW Level Output
Preset to Q
13.5
17
ns
(Clock HIGH)
t
PHL
Propagation Delay Time
Preset to Q
8
14
ns
HIGH-to-LOW Level Output
(Clock LOW)
Propagation Delay Time
t
PHL
Clear to Q
13.5
16
ns
HIGH-to-LOW Level Output
(Clock HIGH)
Propagation Delay Time
t
PHL
Clear to Q
8
13
ns
HIGH-to-LOW Level Output
(Clock LOW)
t
PLH
Propagation Delay Time
LOW-to-HIGH Level Output
Clock to Q or Q
9
12
ns
t
PHL
Propagation Delay Time
HIGH-to-LOW Level Output
Clock to Q or Q
9
14
ns
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