參數(shù)資料
型號(hào)： DM9161
廠商： Electronic Theatre Controls, Inc.
英文描述： 10/100 Mbps FAST ETHERNET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER
中文描述： 10/100 Mbps快速以太網(wǎng)物理層單芯片收發(fā)器
文件頁數(shù)： 2/47頁
文件大?。?/td> 561K
代理商： DM9161
DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
2
Final
Version: DM9161-DS-F02
May 10,2002
Table of Contents
1. General Description..............................................3
2. Block Diagram ......................................................3
3. Features................................................................4
4. Pin Configuration: DM9161 LQFP ........................5
5. Pin Description......................................................6
5.1 Normal MII Interface, 21 pins..............................6
5.2 Media Interface, 4 pins........................................8
5.3 LED Interface, 3 pins ..........................................8
5.4 Mode, 2 pins .......................................................8
5.5 Bias and Clock, 4 pins ........................................9
5.6 Power, 13 pins....................................................9
5.7 Table A................................................................9
5.8 Pin Maps of Normal MII, Reduced MII, and
10Base-T GPSI (7-Wired) Mode..................... 10
6. LED Configuration...............................................11
7. Functional Description ........................................12
7.1 MII interface......................................................12
7.2 100Base-TX Operation.....................................14
7.2.1 100Base-TX Transmit....................................14
7.2.1.1 4B5B Encoder.............................................15
7.2.1.2 Scrambler ...................................................15
7.2.1.3 Parallel to Serial Converter.........................15
7.2.1.4 NRZ to NRZI Encoder.................................15
7.2.1.5 MLT-3 Converter.........................................15
7.2.1.6 MLT-3 Driver...............................................15
7.2.1.7 4B5B Code Group.......................................16
7.2.2 100Base-TX Receiver....................................17
7.2.2.1 Signal Detect...............................................17
7.2.2.2 Adaptive Equalizer......................................17
7.2.2.3 MLT-3 to NRZI Decoder .............................17
7.2.2.4 Clock Recovery Module..............................18
7.2.2.5 NRZI to NRZ...............................................18
7.2.2.6 Serial to Parallel..........................................18
7.2.2.7 Descrambler ...............................................18
7.2.2.8 Code Group Alignment ...............................18
7.2.2.9 4B5B Decoder.............................................18
7.2.3 10Base-T Operation ......................................18
7.2.4 Collision Detection.........................................18
7.2.5 Carrier Sense.................................................18
7.2.6 Auto-Negotiation............................................18
7.2.7 MII Serial Management..................................19
7.2.8 Serial Management Interface.........................19
7.2.9 Management Interface – Read Frame
Structure .........................................................19
7.2.10 Management Interface – Write Frame
Structure........................................................19
7.2.11 Power Reduced Mode .................................20
7.2.12 Power Down Mode.......................................20
7.2.13 Reduced Transmit Power Mode..................20
8. MII Register Description......................................21
8.1 Basic Mode Control Register (BMCR) - 00.......22
8.2 Basic Mode Status Register (BMSR) - 01 ........23
8.3 PHY ID Identifier Register #1 (PHYIDR1) - 02..24
8.4 PHY ID Identifier Register #2 (PHYIDR2) - 03..24
8.5 Auto-negotiation Advertisement Register (ANAR)
- 04 ...................................................................25
8.6 Auto-negotiation Link Partner Ability Register
(ANLPAR) - 05 .................................................26
8.7 Auto-negotiation Expansion Register (ANER)
- 06 ...................................................................27
8.8 DAVICOM Specified Configuration Register
(DSCR) –16.......................................................27
8.9 DAVICOM Specified Configuration and Status
Register (DSCSR) - 17.....................................29
8.10 10Base-T Configuration / Status (10BTCSR) - 18
.........................................................................30
8.11 DAVICOM Specified Interrupt Register - 21 ...30
8.12 DAVICOM Specified Receive Error Counter
Register (RECR) - 22.......................................31
8.13 DAVICOM Specified Disconnect Counter
Register (DISCR) - 23......................................31
8.14 DAVICOM Hardware Reset Latch State
Register (RLSR) - 24 .......................................31
9. DC and AC Electrical Characteristics
9.1 Absolute Maximum Ratings
(
25
°
C )...................32
9.2 Operating Conditions........................................32
9.3 DC Electrical Characteristics ............................33
9.4 AC Electrical Characteristics & Timing
Waveform ..........................................................33
9.4.1 TP Interface ...................................................33
9.4.2 Oscillator/Crystal Timing................................33
9.4.3 MDC/MDIO Timing ........................................34
9.4.4 MDIO Timing when OUTPUT by STA ...........34
9.4.5 MDIO Timing when OUTPUT by DM9161.....34
9.4.6 100Base-TX Transmit Timing Parameters....35
9.4.7 100Base-TX Transmit Timing Diagram.........35
9.4.8 100Base-TX Receive Timing Parameters.....35
9.4.9 MII 100Base-TX Receive Timing Diagram ....36
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