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參數(shù)資料
| 型號： | DM9374 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 7-Segment Decoder/Driver/Latch with Constant Current Sink Outputs(恒流耗散輸出的7段顯示譯碼器/驅(qū)動器/鎖存器) |
| 中文描述： | 7段解碼器/驅(qū)動器/接收器輸出恒定電流（恒流耗散輸出的7段顯示譯碼器/驅(qū)動器/鎖存器鎖存） |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 91K |
| 代理商： | DM9374 |
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www.fairchildsemi.com
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Functional Description
The DM9374 is a 7-segment decoder/driver with latches on
the address inputs and active LOW constant current out-
puts to drive LEDs directly. This device accepts a 4-bit
binary code and produces output drive to the appropriate
segments of the 7-segment display. It has a decode format
which produces numeric codes “0” through “9” and other
codes.
Latches on the four data inputs are controlled by an active
LOW Latch Enable, LE. When LE is LOW, the state of the
outputs is determined by the input data. When LE goes
HIGH, the last data present at the inputs is stored in the
latches and the outputs remain stable. The LE pulse width
necessary to accept and store data is typically 50 ns, which
allows data to be strobed into the DM9374 at normal TTL
speeds. This feature means that data can be routed
directly from high speed counters and frequency dividers
into the display without slowing down the system clock or
providing intermediate data storage.
The latch/decoder combination is a simple system which
drives LED displays with multiplexed data inputs from MOS
time clocks, DVMs, calculator chips, etc. Data inputs are
multiplexed while the displays are in static mode. This low-
ers component and insertion costs, since several circuits—
seven resistors per display, strobe drivers, a separate dis-
play voltage source, and clock failure detect circuits—tradi-
tionally found in multiplexed display systems are
eliminated. It also allows low strobing rates to be used with-
out display flicker.
Another DM9374 feature is the reduced loading on the
data inputs when the Latch Enable is HIGH (only 10
μ
A
typ). This allows many DM9374s to be driven from a MOS
device in multiplex mode without the need for drivers on
the data lines. The DM9374 also provides automatic blank-
ing of the leading and/or trailing-edge zeroes in a multidigit
decimal number, resulting in an easily readable decimal
display conforming to normal writing practice. In an 8-digit
mixed integer fraction decimal representation, using the
automatic blanking capability 0060.0300 would be dis-
played as 60.03. Leading-edge zero suppression is
obtained by connecting the Ripple Blanking Output (RBO)
of a decoder to the Ripple Blanking Input (RBI) of the next
lower stage device. The most significant decoder stage
should have the RIB input grounded; and since suppres-
sion of the least significant integer zero in a number is not
usually desired, the RBI input of this decoder stage should
be left open. A similar procedure for the fractional part of a
display will provide automatic suppression of trailing-edge
zeroes. The RBO terminal of the decoder can be OR-tied
with a modulating signal via an isolating buffer to achieve
duration intensity modulation. A suitable signal can be gen-
erated for this purpose by forming a variable frequency
multivibrator with a cross coupled pair of TTL or DTL gates.
Logic Diagram
相關PDF資料 |
PDF描述 |
|---|---|
| DM9374N | 7-Segment Decoder/Driver/Latch with Constant Current Sink Outputs |
| DM93L14 | Quad Latch(四鎖存器) |
| DM93L14N | Quad Latch |
| DM93L28 | Dual 8-Bit Shift Register(雙8位移位寄存器) |
| DM93L28N | Dual 8-Bit Shift Register |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DM9374N | 功能描述:編碼器、解碼器、復用器和解復用器 7-Seg Dec/Drv/Latch RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| DM9386 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:4-Bit Quad Exclusive-NOR with Open-Collector Outputs |
| DM93L00 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| DM93L01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| DM93L08 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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