參數(shù)資料
型號(hào)： DM93L01
文件頁數(shù)： 3/158頁
文件大小： 2668K
代理商： DM93L01
TL/F/6600
9
June 1989
9300/DM9300 4-Bit Parallel-Access Shift Register
General Description
The 9300 4-bit registers feature parallel inputs, parallel out-
puts, JK serial inputs, shift/load control input, and a direct
overriding clear. The registers have two modes of operation:
parallel (broadside) load and shift (in direction Q
A
toward
Q
D
).
Parallel loading is accomplished by applying the four bits of
data and taking the shift/load control input low. The data is
loaded into the associated flip-flops, and appears at the out-
puts after the positive transition of the clock input. During
loading, serial data flow is inhibited.
Shifting is accomplished synchronously when the shift/load
control input is high. Serial data for this mode is entered at
the JK inputs. These inputs permit the first stage to perform
as a JK, D or T-type flip-flop as shown in the function table.
These shift registers are fully compatible with most other
TTL and DTL families. All inputs, including the clock, are
buffered to lower the drive requirements to one normalized
Series 54/74 load.
Features
Y
Fully buffered inputs
Y
Direct overriding clear
Y
Synchronous parallel load
Y
Parallel inputs and outputs from each flip-flop
Y
Positive edge-triggered clocking
Y
J and K inputs to first stage
Y
Typical shift frequencyD39 MHz
Connection Diagram
Dual-In-Line Package
TL/F/6600–1
Order Number 9300DMQB,
9300FMQB or DM9300N
See NS Package Number
J16A, N16E or W16A
Function Table
Inputs
Outputs
Clear
Shift/
Load
Clock
Serial
Parallel
Q
A
Q
B
Q
C
Q
D
Q
D
J
K
P0
P1
P2
P3
L
H
H
H
H
H
H
X
L
H
H
H
H
H
X
u
L
u
u
u
u
X
X
X
L
L
H
H
X
X
X
H
L
H
L
X
a
X
X
X
X
X
X
b
X
X
X
X
X
X
c
X
X
X
X
X
X
d
X
X
X
X
X
L
a
L
b
L
c
L
d
H
d
Q
A0
Q
A0
L
H
Q
An
Q
B0
Q
A0
Q
An
Q
An
Q
An
Q
C0
Q
Bn
Q
Bn
Q
Bn
Q
Bn
Q
D0
Q
Cn
Q
Cn
Q
Cn
Q
Bn
Q
D0
Q
Cn
Q
Cn
Q
Cn
Q
Cn
H
e
High Level (Steady State)
L
e
Low Level (Steady State)
X
e
Don’t Care
u
e
Transition from low-to-high level
a, b, c, d,
e
The level of steady state input at P0, P1, P2, or P3 respectively.
Q
A0
, Q
B0
, Q
C0
, Q
D0
e
The level of Q
A
, Q
B
, Q
C
, or Q
D
, respectively before the indicated steady state input conditions were established.
Q
An
, Q
Bn
, Q
Cn
e
The level of Q
A
, Q
B
, Q
C
, respectively, before the most recent
u
transition of the clock.
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
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