參數(shù)資料
型號: DM93L14N
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Quad Latch
中文描述: 93L SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP14
封裝: 0.300 INCH, PLASTIC, MS-001, DIP-14
文件頁數(shù): 4/5頁
文件大?。?/td> 115K
代理商: DM93L14N
www.fairchildsemi.com
4
D
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Note 2:
All typicals are at V
CC
=
5V, T
A
=
25
°
C
Note 3:
Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 4:
I
CC
is measured with all outputs open and all inputs grounded.
Switching Characteristics
V
CC
=
+
5.0V, T
A
=
+
25
°
C (See Waveforms and Load Configurations)
Symbol
Parameter
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 2)
V
I
V
OH
Input Clamp Voltage
HIGH Level Output Voltage
V
CC
=
Min, I
I
=
10 mA
V
CC
=
Min, I
OH
=
Max,
V
IL
=
Max, V
IH
=
Min
V
CC
=
Min, I
OL
=
Max,
V
IH
=
Min, V
IL
=
Max
V
CC
=
Max, V
I
=
5.5V
1.5
V
2.4
V
V
OL
LOW Level Output Voltage
0.3
V
I
I
Input Current @ Max
Input Voltage
HIGH Level Input Current
1
mA
I
IH
V
CC
=
Max, V
I
=
2.4V
Inputs
20
μ
A
D
n
Inputs
D
n
30
I
IL
LOW Level Input Current
V
CC
=
Max, V
I
=
0.3V
400
600
μ
A
I
OS
Short Circuit
Output Current
Supply Current
V
CC
=
Max
(Note 3)
V
CC
=
Max (Note 4)
2.5
25
mA
I
CC
16.5
mA
Min
Max
Units
t
PLH
t
PHL
t
PLH
t
PHL
Propagation Delay
E to Q
n
Propagation Delay
45
36
30
ns
ns
D
n
to Q
n
30
t
PLH
Propagation Delay, MR to Q
n
30
ns
t
PHL
Propagation Delay, S
n
to Q
n
33
ns
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