參數(shù)資料
型號: DM93L21
文件頁數(shù): 55/158頁
文件大?。?/td> 2668K
代理商: DM93L21
Switching Characteristics
V
CC
= +5.0V, T
A
= +25C (See Section 1 for waveforms and load configurations)
Symbol
Parameter
C
L
= 15 pF
Units
Min
Max
14
14
25
22
26
21
30
32
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Propagation Delay
E to A = B
Propagation Delay
A
n
, B
n
to A
>
B
Propagation Delay
A
n
, B
n
to A
<
B
Propagation Delay
A
n
, B
n
to A = B
ns
ns
ns
ns
Functional Description
The ’24 5-bit comparators use combinational circuitry to di-
rectly generate “A greater than B” and “A less than B” out-
puts. As evident from the logic diagram, these outputs are
generated in only three gate delays. The “A equals B” output
is generated in one additional gate delay by decoding the “A
neither less than nor greater than B” condition with a NOR
gate. All three outputs are activated by the active LOW En-
able Input (E).
Truth Table
Tying theA
>
B output from one device into anAinput on an-
other device and the A
<
B output into the corresponding B
input permits easy expansion.
The A4 and B4 inputs are the most significant inputs and A0,
B0 the least significant. Thus if A4 is HIGH and B4 is LOW,
the A
>
B output will be HIGH regardless of all other inputs
except E .
Inputs
A
n
X
Word A = Word B
Word A
>
Word B
Word B
>
Word A
Outputs
A
>
B
L
L
H
L
E
H
L
L
L
B
n
X
A
<
B
L
L
L
H
A = B
L
H
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Logic Symbol
DS009792-2
V
= Pin 16
GND = Pin 6
3
www.fairchildsemi.com
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