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參數(shù)資料
| 型號： | DM93L38 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 8-Bit Multiple Port Register(8位多端口寄存器) |
| 中文描述： | 8位多端口寄存器（8位多端口寄存器） |
| 文件頁數(shù)： | 2/6頁 |
| 文件大小： | 64K |
| 代理商： | DM93L38 |
www.fairchildsemi.com
2
D
Functional Description
The DM93L38 8-bit multiple port register can be consid-
ered a 1-bit slice of eight high speed working registers.
Data can be written into any one and read from any two of
the eight locations simultaneously. Master/slave operation
eliminates all race problems associated with simultaneous
read/write activity from the same location. When the clock
input (CP) is LOW data applied to the data input line (D
A
)
enters the selected master. This selection is accomplished
by coding the three write input select lines (A0
–
A2) appro-
priately. Data is stored synchronously with the rising edge
of the clock pulse.
The information for each of the two slaved (output) latches
is selected by two sets of read address inputs (B0
–
B2 and
C0
–
C2). The information enters the slave while the clock is
HIGH and is stored while the clock is LOW. If Slave Enable
is LOW (SLE), the slave latches are continuously enabled.
The signals are available on the output pins (Z
B
and Z
C
).
The input bit selection and the two output bit selections can
be accomplished independently or simultaneously. The
data flows into the device, is demultiplexed according to
the state of the write address lines and is clocked into the
selected latch. The eight latches function as masters and
store the input data. The two output latches are slaves and
hold the data during the read operation. The state of each
slave is determined by the state of the master selected by
its associated set of read address inputs.
The method of parallel expansion is shown in Figure 1.
One DM93L38 is needed for each bit of the required word
length. The read and write input lines should be connected
in common on all of the devices. This register configuration
provides two words of n-bits each at one time, where n
devices are connected in parallel.
FIGURE 1. Parallel Expansion
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| DM93L38N | 功能描述:寄存器 DISC BY MFG 7/03 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| DM93S41 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:4-Bit Arithmetic Logic Unit |
| DM93S41N | 功能描述:算數(shù)邏輯單元 - ALU 4-Bit Arith Log Unit RoHS:否 制造商:ON Semiconductor 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:18 V 電源電壓-最小:3 V 封裝 / 箱體:SOIC-16 Wide 最大工作溫度:+ 125 C 封裝:Reel |
| DM93S43 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:4-BIT BY 2-BIT TWOS COMPLEMENT MULTIPLIER |
| DM93S43N | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:4-BIT BY 2-BIT TWOS COMPLEMENT MULTIPLIER |
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