參數(shù)資料
型號(hào): DMA2280
英文描述: Consumer IC
中文描述: 消費(fèi)性IC
文件頁數(shù): 24/36頁
文件大?。?/td> 496K
代理商: DMA2280
DMA 2271, DMA 2280, DMA 2281
24
3.3.5. The
Φ
A Audio Clock
The audio clock
Φ
A for the AMU 2481 Audio Mixer and
the ACP 2371 Audio Processor is also supplied by the
DMA 2271, DMA 2280 and DMA 2281 which generate
this 18.432 MHz clock by means of the crystal con-
nected to pins 16 and 17 and supply it via pin 65. The fre-
quency of 18.432 MHz is an integer multiple of the sound
sampling frequency (32 kHz).
The
Φ
A audio clock output pin 65 can be switched over
to the normal main clock
Φ
M if a standard other than C/
D/D2–MAC is received. For this, bit ACS in address 204
of the IM bus is provided (Table 4–1).
The clock frequency
Φ
S for the serial S bus is also
derived from the audio clock
Φ
A (pin 65) by dividing by
eight (18.432 MHz: 4 = 4.608 MHz)
3.3.6. The Buffer for Packet 0
One packet address (000H) is reserved for service and
network identification data. A 720–bit (90 Byte) Buffer is
implemented on–chip especially for this, and is con-
trolled by the CCU via the IM bus (bits 8 and 9, address
204). The following conditions must be met to ensure
that a received packet is stored in this buffer:
Packet Address
Packet Type
Data Group Type TG = selected type in IM bus
PA = 000H
PT = F8H
register 204
Packet 0 Status
P0 = 0 (see IM bus registers 204
and 206)
The packet 0 buffer can be read sequentially from a
16–bit IM bus register (address 210, Table 4–2). One
complete read cycle takes about 1.5 ms (IM bus fre-
quency = 1 MHz). It is possible to reset and to clear the
buffer via the IM bus in order to repeat the last–read
cycle or to receive the next zero packet. Additionally, the
last 16 bits of the zero packet are used for error check-
ing. This CRC check calculates the 16–bit syndrom vec-
tor of the packet concerned and stores it in an IM bus
register. It can then be used by software for error detec-
tion.
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