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參數(shù)資料
| 型號： | DMA2281 |
| 英文描述： | Consumer IC |
| 中文描述： | 消費性IC |
| 文件頁數(shù)： | 6/36頁 |
| 文件大小： | 496K |
| 代理商： | DMA2281 |
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DMA 2271, DMA 2280, DMA 2281
6
51
Combined Output for Horizon-
tal and Vertical Blanking
CBL
52
Data Burst Window Output
DBW
53
Composite Sync Output
CSYNC
54
Test Input/Output
T0
55
Packet Data Output
PDAT
56
Descrambled Packet Data In-
put
DPDAT
57
Teletext Sync Output
TSYNC
58
Burst Sync Output
BSYNC
59
Burst Data Input/Output
BDAT
60
Burst Clock Output
BCLK
61
Ground
GND
62
Main Clock Input
MCLK
63
Supply Voltage
V
SUP
64
Sound Bus Ident Output
SBI
65
Audio Clock Output
ACLK
66
Sound Bus Data Output
SBD
67
Sound Bus Clock Output
SBC
68
Column Address Select Out-
put
CASQ
2.3. Pin Descriptions
Pin 1 – RAM Data Input/Output RDAT (Fig. 2–7)
serves as an output for writing data into the external
RAM and as an input for reading data from the external
RAM.
Pins 2 to 6 and 9 to 11 – RAM Address Outputs RA0 to
RA7 (Fig. 2–10)
These pins are used for addressing the external RAM.
Pin 7 – RAM Read/Write Output R/WQ (Fig. 2–10)
By means of this output the external RAM is switched to
read or write mode.
Pin 8 – Row Address Select Output RASQ (Fig. 2–10)
This pin supplies the Row Address Select signal to the
Pins 12 to 14 – IM Bus Connection IMC, IMI,IMD (Figs.
2–2 and 2–6)
These pins connect the DMA 2271, DMA 2280 and DMA
2281 to the IM bus. Via the IM bus the DMA 2271, DMA
2280 and DMA 2281 communicate with the CCU 3000
Central Control unit. The data transferred via the IM bus
are listed in tables 4–1 to 4–4.
Pin 15 – Reset Input RESQ (Fig. 2–5)
Pin 15 is used for hardware reset. Reset is actuated at
Low level, at High level the DMA 2271, DMA 2280, and
DMA 2281 are ready for operation.
Pins 16 and 17 – XTAL 1 Output and XTAL 2 Input (Fig.
2–11)
These oscillator pins are used to connect an 18.432
MHz crystal, which determines the ACLK audio clock
signal supplied by pin 65. Alternatively, an 18.432 MHz
clock may be fed to pin 17.
Pin 18 – Output Disable Input ODI
This input serves for fast switchover of the luma and
chroma outputs (L0 to L7 and C0 to C7) to high imped-
ance, which is required if the TV receiver is equipped
with Picture–in–picture. Low means outputs active, High
means outputs are disabled.
Pin 19 – leave vacant
Pin 20 – leave vacant
Pins 21 to 24 and 27 to 30 – Chroma Outputs C7 to C0
(Fig. 2–8)
Via these pins, the DMA 2271, DMA 2280, and DMA
2281 deliver the digital chrominance signal (R–Y, B–Y)
in multiplexed operation to the VCU 2133 Video Codec
Unit, where it is converted to an analog signal.
Pin 25 – PLL Tuning Data Output PLLD (Fig. 2–8)
This pin supplies the 12–bit data word containing the
PLL tuning information from the PLL filter of the DMA
2271, DMA 2280, and DMA 2281. This information is
needed by the voltage controlled oscillator (VCO) con-
tained on the MCU 2600 Clock Generator IC and closes
the PLL which determines the main clock signal.
Pin 26 – PLL Tuning Clock Output PLLC (Fig. 2–8)
This pin supplies the data clock signal needed for the se-
rial data transfer of the 12–bit PLL tuning information.
Pins 31 to 38 – Luma Outputs L0 to L7 (Fig. 2–8)
Via these pins, the DMA 2271, DMA 2280 and DMA
2281 deliver the digital luminance signal to the VCU
2133 Video Codec Unit, where it is converted to an ana-
log signal.
Pins 39 to 46 – Baseband Input BI7 to BI0 (Fig. 2–3)
Via these inputs, the DMA 2271, DMA 2280, and DMA
2281 receive the digitized baseband signal from the
VCU 2133 Video Codec.
Pin 47 – leave vacant
Pin 48 – Clamping Output CLMP (Fig. 2–9)
This pin supplies a PDM (Pulse Density Modulated) sig-
nal for clamping the analog baseband signal at the input
of the analog to digital converter.
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