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參數(shù)資料
| 型號(hào)： | DOC4106 |
| 廠商： | Atmel Corp. |
| 英文描述： | Single-Chip Microcontroller with MP3 Decoder and Man-Machine Interface |
| 中文描述： | 單片微控制器，帶有MP3解碼器和人機(jī)界面 |
| 文件頁數(shù)： | 22/47頁 |
| 文件大?。?/td> | 791K |
| 代理商： | DOC4106 |
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AT8xC51SND1C
4106F–8051–10/02
Peripherals
Clock Generator System
The AT8xC51SND1C internal clocks are extracted from an on-chip PLL fed by an on-
chip oscillator. Four clocks are generated respectively for the C51 core, the MP3
decoder, the audio interface, and the other peripherals. The C51 and peripheral clocks
are derived from the oscillator clock. The MP3 decoder clock is generated by dividing
the PLL output clock. The audio interface sample rates are also obtained by dividing the
PLL output clock.
Ports
The AT8xC51SND1C implement five 8-bit ports (P0 - P4) and one 4-bit port (P5). In
addition to performing general-purpose I/Os, some ports are capable of external data
memory operations; others allow for alternate functions. All I/O Ports are bi-directional.
Each Port contains a latch, an output driver and an input buffer. Port 0 and Port 2 output
drivers and input buffers facilitate external memory operations. Some Port 1, Port 3 and
Port 4 pins serve for both general-purpose I/Os and alternate functions.
Timers/Counters
The AT8xC51SND1C implement the two general-purpose, 16-bit Timers/Counters of a
standard C51. They are identified as Timer 0, Timer 1, and can independently be config-
ured each to operate in a variety of modes as a Timer or as an event Counter. When
operating as a Timer, a Timer/Counter runs for a programmed length of time, then
issues an interrupt request. When operating as a Counter, a Timer/Counter counts neg-
ative transitions on an external pin. After a preset number of counts, the Counter issues
an interrupt request.
Watchdog Timer
The AT8xC51SND1C implement a hardware Watchdog Timer that automatically resets
the chip if it is allowed to time out. The WDT provides a means of recovering from rou-
tines that do not complete successfully due to software or hardware malfunctions.
MP3 Decoder
The AT8xC51SND1C implements a MPEG I/II audio layer 3 decoder (MP3 decoder).
In MPEG I (ISO 11172-3) three layers of compression have been standardized support-
ing three sampling frequencies: 48, 44.1, and 32 kHz. Among these layers, layer 3
allows highest compression rate of about 12:1 while still maintaining CD audio quality.
For example, 3 minutes of CD audio (16-bit PCM, 44.1 kHz) data, which needs about
32M bytes of storage, can be encoded into only 2.7 MBytes of MPEG I audio layer 3
data.
In MPEG II (ISO 13818-3), three additional sampling frequencies: 24, 22.05, and 16 kHz
are supported for low bit rates applications.
The AT8xC51SND1C can decode in real-time the MPEG I audio layer 3 encoded data
into a PCM audio data, and also supports MPEG II audio layer 3 additional frequencies.
Additional features are supported by the AT8xC51SND1C MP3 decoder such as vol-
ume, bass, medium, and treble controls, bass boost effect and ancillary data extraction.
Audio Output Interface
The AT8xC51SND1C implements an audio output interface allowing the decoded audio
bitstream to be output in various formats. It is compatible with right and left justification
PCM and I
2
S formats and the on-chip PLL (see Section “Clock Generator System”)
allows connection of almost all of the commercial audio DAC families available on the
market.
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