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參數(shù)資料
| 型號(hào)： | DP3S1MX32PY5-10CI |
| 英文描述： | x32 SRAM Module |
| 中文描述： | X32號(hào)的SRAM模塊 |
| 文件頁(yè)數(shù)： | 6/6頁(yè) |
| 文件大?。?/td> | 510K |
| 代理商： | DP3S1MX32PY5-10CI |
DP3S1MX32PY5
Dense-Pac Microsystems, Inc.
AD VANCED IN FOR MA TION
6
30A244-00
REV. A
ME CHAN CAL DRAWING
OR DERING IN FOR MA TION
Dense-Pac Microsystems, Inc.
7321 Lincoln Way, Garden Grove, California 92841-1431
(714) 898-0007
u
(800) 642-4477
u
FAX: (714) 897-1772
u
http://www.dense-pac.com
NOTES:
1.
2.
3.
4.
All voltages are with respect to V
SS
.
-1.5V min. (Pulse Width
≤
4ns) for I
≤
20mA.
V
IH
(max.)= V
DD
+ 1.5Vdc (Pulse Width
≤
4ns) for I
≤
20mA.
Stresses greater than those under
ABSOLUTE MAXIMUM
RATINGS
may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
5.
6.
This parameter is guaranteed and not 100% tested.
Transition is measured at the point of
±
500mV from steady
state voltage.
When OE and CE are LOW and WE is HIGH, I/O pins are in
the output state,and input signals of opposite phase to the
outputs must not be applied.
The outputs are in a high impedance state when WE is
LOW.
Chip Enable and Write Enable can initiate and terminate
WRITE Cycle.
7.
7.
9.
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