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參數(shù)資料
| 型號： | DP8238 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 137K |
| 代理商： | DP8238 |
Capacitance
*
V
BIAS
e
2.5V, V
CC
e
5.0V, T
A
e
25
§
C, f
e
1 MHz
Symbol
Parameter
Min
Typ
Max
Units
(Note 1)
C
IN
Input Capacitance
8
12
pF
C
OUT
Output Capacitance Control Signals
7
15
pF
I/O
I/O Capacitance (D or DB)
8
15
pF
*
This parameter is periodically sampled and not 100% tested.
Switching Characteristics
Min
s
V
CC
s
Max, Min
s
T
A
s
Max
DP8228M,
DP8238M
DP8228,
DP8238
Symbol
Parameter
Conditions
Units
Min
Max
Min
Max
t
PW
Width of Status Strobe
25
22
ns
t
SS
Set-Up Time, Status Inputs D0–D7
8
8
ns
t
SH
Hold Time, Status Inuts D0–D7
5
5
ns
t
DC
Delay from STSTB to Any Control Signal
(Figure 2)
20
75
20
60
ns
t
RR
Delay from DBIN to Control Outputs
(Figure 2)
30
30
ns
t
RE
Delay from DBIN to Enable/
Disable 8080 Bus
(Figure 1)
45
45
ns
t
RD
Delay from System Bus to 8080
Bus During Read
(Figure 1)
45
30
ns
t
WR
Delay from WR to Control Outputs
(Figure 2)
5
60
5
45
ns
t
WE
Delay to Enable System Bus
DB0–DB7 after STSTB
(Figure 2)
30
30
ns
t
WD
Delay from 8080 Bus D0–D7 to
System Bus DB0–DB7 During Write
(Figure 2)
5
40
5
40
ns
t
E
Delay from System Bus Enable to
System Bus DB0–DB7
(Figure 2)
30
30
ns
t
HD
HLDA to Read Status Outputs
(Figure 2)
25
25
ns
t
DS
Set-Up Time, System Bus Inputs to HLDA
10
10
ns
t
DH
Hold Time, System Bus Inputs to HLDA
20
20
ns
Test Conditions
TL/F/6825–2
TL/F/6825–3
TL/F/6825–4
FIGURE 1. Test Load
FIGURE 2. Test Load
FIGURE 3. INTA Test Circuit
(For RST 7)
3
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| DP8238M | |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DP8238J | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:System Controller and Bus Driver |
| DP8238J/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:System Controller |
| DP8238M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| DP8238MJ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:System Controller and Bus Driver |
| DP8238MJ/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:System Controller |
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