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參數資料
| 型號： | DP8238M |
| 文件頁數： | 4/6頁 |
| 文件大?。?/td> | 137K |
| 代理商： | DP8238M |
Timing Diagram
TL/F/6825–5
VOLTAGE MEASUREMENT POINTS:
D
0
–D
7
(when outputs) Logic ‘‘0’’
e
0.8V, Logic ‘‘0’’
e
0.8V, Logic ‘‘1’’
e
3.0V. All other signals measured at 1.5V.
*
Advanced I/OW MEMW for 8238 only.
Functional Pin Definitions
The following describes the function of all of the DP8228/
DP8228M, DP8238/DP8238M pinouts. Some of these de-
scriptions reference internal circuits.
INPUT SIGNALS
Status Strobe (STSTB):
Activated (low) at the start of each
new machine cycle. The STSTB input is used to store a
status word (refer to chart) from the 8080A microprocessor
into the internal status latch of the DP8228, DP8238. The
status word is latched when the STSTB returns to the high
state. The 8080A outputs this status word onto its data bus
during the first state (SYNC interval) of each machine cycle.
Data Bus In (DBIN):
When high, indicates that the 8080A
data bus is in the input mode. The DBIN signal is used to
gate data from memory or an input/output device onto the
data bus.
Write (WR):
When low, indicates that the data on the
8080A data bus are stable for WRITE memory or output
operation.
Hold Acknowledge (HLDA):
When high, indicates that the
8080A data and address buses will go to their high imped-
ance state. When in the data bus read mode, DBIN input in
the high state, a high HLDA input will latch the data bus
information into the driver circuits and gate off the applica-
ble control signal I/OR, MEMR, or INTA (return to the out-
put high state).
Bus Enable (BUSEN):
Asynchronous DMA input to the in-
ternal gating array. When low, normal operation of the inter-
nal bidirectional bus driver and gating array occurs. When
high, the bus driver and gating array are driven to their high
impedance state.
V
CC
Supply:
a
5V.
Ground:
0V reference.
OUTPUT SIGNALS
Memory Read (MEMR):
When low, signals data to be load-
ed in from memory. The MEMR signal is generated by strob-
ing in status word 1, 2, or 4. (Refer to status word chart.)
Memory Write (MEMW):
When low, signals data to be
stored in memory. The MEMW signal is generated for the
DP8238 by strobing in status word 3 or 5. (Refer to status
word chart.) For the DP8228, the MEMW signal is generated
by gating a low-level WR input with the strobed in status
word 3 or 5.
Input/Output Read (I/OR):
When low, signals data to be
loaded in from an addressed input/output device. The I/OR
signal is generated by strobing in status word 6.
Input/Output Write (I/OW):
When low, signals data to be
transferred to an addressed input/output device. The I/OW
signal for the DP8238 is generated by strobing in status
word 7. For the DP8238 the I/OW signal is generated by
gating in a low-level WR input with the strobed in status
word 7.
Interrupt Acknowledge (INTA):
When low, indicates that
an interrupt has been acknowledged by the 8080A micro-
processor. The INTA signal is generated by strobing in
staus word 8 or 10.
Signal Level Interrupt (RST 7):
When the INTA output is
tied to 12V through a 1 k
X
resistor, strobing in status word 8
or 10 will cause the CPU data bus outputs, when active, to
go to the high state.
INPUT/OUTPUT SIGNALS
CPU Data (D
7
–D
0
) Bus:
This bus comprises eight
TRI-STATE
é
input/output lines that connect to the 8080A
microprocessor. The bus provides bidirectional communica-
4
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相關代理商/技術參數 |
參數描述 |
|---|---|
| DP8238MJ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:System Controller and Bus Driver |
| DP8238MJ/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:System Controller |
| DP8238N | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:System Controller and Bus Driver |
| DP8238N/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:System Controller |
| DP8238N/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:System Controller |
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