參數(shù)資料
型號: DP84432J
英文描述: DRAM Controller
中文描述: DRAM控制器
文件頁數(shù): 23/46頁
文件大?。?/td> 644K
代理商: DP84432J
6.0 Refresh Modes
(Continued)
6.4 EXTENDING REFRESH
The programmed number of periods of CLK that refresh
RASs are asserted can be extended by one or multiple peri-
ods of CLK. Only the all RAS (with or without error scrub-
bing) type of refresh can be extended. To extend a refresh
cycle, the input extend refresh, EXTNDRF, must be assert-
ed before the positive edge of CLK that would have negated
all the RAS outputs during the re fresh cycle and after the
positive edge of CLK which starts all RAS outputs during the
refresh as shown inFigure 17. This will extend the refresh to
the next positive edge of CLK and EXTNDRF will be sam-
pled again. The refresh cycle will continue until EXTNDRF is
sampled low on a positive edge of CLK.
TL/F/11718–43
FIGURE 17. Extending Refresh with the Extend Refresh (EXTNDRF) Input
23
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DP84432J/A+ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller
DP84432N 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller
DP84432N/A+ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller
DP84432N/B+ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller
DP8450N-4 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Disk Data Separator/Synchronizer