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參數(shù)資料
| 型號： | DPS1MX16MKJ3-35I |
| 英文描述： | x16 SRAM Module |
| 中文描述： | x16的SRAM模塊 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 746K |
| 代理商： | DPS1MX16MKJ3-35I |
Dense-Pac Microsystems, Inc.
DPS1MX16MKn3
+5V
255
480
C
L
*
D
OUT
Figure 1. Output Load
OUTPUT LOAD
Parameters Measured
except t
LZ
, t
HZ
, t
OHZ
, t
OLZ
, and t
WHZ
t
LZ
, t
HZ
, t
OHZ
, t
OLZ
, and t
WHZ
Load
1
2
C
L
100pF
5pF
AC TEST CONDITIONS
Input Pulse Levels
Input Pulse Rise and Fall Times
Input and Output
Timing Reference Levels
0V to 3.0V
5ns
1.5V
Data Retention AC Characteristics
8
Test Conditions
CE
≥
V
DR
-0.2V
Symbol
V
DR
Parameter
Min.
2.0
Typ.
-
Max.
-
Unit
V
V
DD
for Data Retention
Chip Disable to
Data Retention Time
Operation Recovery Time
V
CDR
See Data Retention Waveform
0
-
-
ns
t
R
See Data Retention Waveform
5
-
-
ms
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE:
Over operating ranges
20ns*
Min.
t
RC
Read Cycle Time
20
t
AA
Address Access Time
t
CO
CE to Output Valid
t
OE
Output Enable to Output Valid
t
LZ
CE to Output in LOW-Z
4, 5
3
t
OLZ
Output Enable to Output in LOW-Z
4, 5
0
t
HZ
CE to Output in HIGH-Z
4, 5
t
OHZ
Output Enable to Output in HIGH-Z
4, 5
0
t
OH
Output Hold from Address Change
4
No. Symbol
Parameter
25ns
30ns
35ns
45ns
Unit
Max.
Min.
25
Max.
Min.
30
Max.
Min.
35
Max.
Min.
45
Max.
1
2
3
4
5
6
7
8
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
10
25
25
12
30
30
15
35
35
20
45
45
25
3
0
3
0
3
0
3
0
8
8
10
10
15
15
20
20
25
25
0
5
0
5
0
5
0
5
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE
6, 7
:
Over operating ranges
20ns*
Min.
t
WC
Write Cycle Time
20
t
AW
Address Valid to End of Write
13
t
CW
Chip Enable to End of Write
13
t
AS
Address Set-Up Time **
0
t
WP
Write Pulse Width
13
t
WR
Write Recovery Time
0
t
WHZ
Write Enable to Output in HIGH-Z
4, 5
0
t
DW
Data to Write Time Overlap
9
t
DH
Data Hold from Write Time
0
t
OW
Output Active from End of Write
3
No. Symbol
Parameter
25ns
30ns
35ns
45ns
Unit
Max.
Min.
25
15
15
0
15
0
0
10
0
3
Max.
Min.
30
20
20
0
20
0
0
12
0
3
Max.
Min.
35
25
25
0
25
0
0
15
0
3
Max.
Min.
45
35
35
0
35
0
0
20
0
3
Max.
10
11
12
13
14
15
16
17
18
19
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
10
12
15
20
* Available in Commercial and Industrial Grade Only.
** Valid for both Read and Write Cycles.
30A129-04
REV. E
3
This Material Copyrighted By Its Respective Manufacturer
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| DPS1MX16MKJ3-35M | x16 SRAM Module |
| DPS1MX16MKJ3-45B | x16 SRAM Module |
| DPS1MX16MKJ3-45C | x16 SRAM Module |
| DPS1MX16MKJ3-45I | x16 SRAM Module |
| DPS1MX16MKJ3-45M | x16 SRAM Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DPS1MX16MKJ3-35M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM Module |
| DPS1MX16MKJ3-45B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM Module |
| DPS1MX16MKJ3-45C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM Module |
| DPS1MX16MKJ3-45I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM Module |
| DPS1MX16MKJ3-45M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM Module |
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