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參數(shù)資料
| 型號(hào)： | DPS1MX32ML-35C |
| 英文描述： | x32 SRAM Module |
| 中文描述： | X32號(hào)的SRAM模塊 |
| 文件頁(yè)數(shù)： | 8/8頁(yè) |
| 文件大?。?/td> | 746K |
| 代理商： | DPS1MX32ML-35C |
DPS1MX16MKn3
Dense-Pac Microsystems, Inc.
ORDERING INFORMATION
Dense-Pac Microsystems, Inc.
7321 Lincoln Way
u
Garden Grove, California 92841-1428
(714) 898-0007
u
(800) 642-4477
(Outside CA)
u
FAX: (714) 897-1772
u
http://www.dense-pac.com
WAVEFORM KEY
Data Valid
Transition from
HIGH to LOW
Transition from
LOW to HIGH
Data Undefined
or Don’t Care
NOTES:
1. All voltages are with respect to V
SS
.
2. -2.0V min. for pulse width less than 20ns (V
IL
min. = -0.5V at DC level).
3. Stresses greater than those under
ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
4. This parameter is guaranteed and not 100% tested.
5. Transition is measured at the point of
±
500mV from steady state voltage.
6. When OE and CE are LOW and WE is HIGH, I/O pins are in the output state,and input signals of opposite
phase to the outputs must not be applied.
7. The outputs are in a high impedance state when WE is LOW.
8. CE and WE can initiate and terminate WRITE Cycle.
30A129-04
REV. E
8
This Material Copyrighted By Its Respective Manufacturer
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