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| 型號： | DPZ256X16IA3-15M |
| 英文描述： | x16 Flash EEPROM Module |
| 中文描述： | x16閃存EEPROM模塊 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 992K |
| 代理商： | DPZ256X16IA3-15M |
DPZ256X32IV3
Dense-Pac Microsystems, Inc.
DEVICE OPERATION:
The FLASH devices are electrically erasable and
programmable memories that function similarly to an
EPROM device, but can be erased without being removed
from the system and exposed to ultraviolet light. Each 128K
x 8 device can be erased individually eliminating the need to
re-program the entire module when partial code changes are
required.
READ:
With V
= 0V to V
(V
)
, the devices are read-only
memories and can be read like a standard EPROM. By
selecting the device to be read
(see Truth Table and
Functional Block Diagram)
, the data programmed into the
device will appear on the appropriate I/O pins.
When V
= +12.0V
±
0.6V
(V
)
, reads can be
accomplished in the same manner as described above but
must be preceded by writing 00H
to the command register
prior to reading the device. When V
is raised to V
the
contents of the command register default to 00H
and remain
that way until the command register is altered.
STANDBY:
When the appropriate CE‘s are raised to a logic-high level,
the standby operation disables the FLASH devices reducing
the power consumption substantially. The outputs are placed
in a high- impedance state, independent of the OE input. If
the module is deselected during programming or erase, the
device upon which the operation was being performed will
continue to draw active current until the operation is
completed.
PROGRAM:
The programming and erasing functions are accessed via the
command register when high voltage is applied to V
. The
contents of the command register control the functions of the
memory device
(see Command Definition Table)
.
The command register is not an addressable memory
location. The register stores the address, data, and command
information required to execute the command. When V
PP
=
V
the command register is reset to 00H
returning the
device to the read-only mode.
The command register is written by enabling the device upon
which that the operation is to be performed
(see Functional
Block Diagram)
. While the device is enabled bring WE to a
logic-low (V
IL
). The address is latched on the falling edge of
WE and data is latched on the rising edge of WE.
Programming is initiated by writing 40H
(program setup
command)
to the command register. On the next falling edge
of WE the address to be programmed will be latched,
followed by the data being latched on the rising edge of WE
(see AC Operating and Characteristics Table)
.
PROGRAM VERIFY:
The FLASH devices are programmed one location at a time.
Each location may be programmed sequentially or at random.
Following each programming operation, the data written
must be verified.
To initiate the program-verify mode, C0H
1
must be written to
the command register of the device just programmed. The
programming operation is terminated on the rising edge of
WE. The program-verify command is then written to the
command register.
After the program-verify command is written to the command
register, the memory device applies an internally generated
margin voltage to the location just written. After waiting 6
μ
s
the data written can be verified by doing a read. If true data
is read from the device, the location write was successful and
the next location may be programmed.
If the device fails to verify, the program/verify operation is
repeated up to 25 times.
ERASE:
The erase function is a command-only operation and can only
be executed while V
PP
= V
PPHI
.
To setup the chip-erase, 20H
1
must be written to the
command register. The chip-erase is then executed by once
again writing 20H
to the command register
(see AC
Operating and Characteristics Table)
.
To ensure a reliable erasure, all bits in the device to be erased
should be programmed to their charged state
(data = 00H)
prior to starting the erase operation. With the algorithm
provided, this operation should typically take 2 seconds.
HIGH PERFORMANCE PARALLEL ERASURE:
Dense-Pac recommends that all users implement the
following Intel High Performance Parallel Erase algorithm
in order to avoid the possibility of over erasing these parts.
In applications containing more than one FLASH memory,
you can erase each device serially or you can reduce total
erase time by implementing a parallel erase algorithm. You
may save time by erasing all devices at the same time.
However, since FLASH memories may erase at different rates,
you must verify each device separately. This can be done in
a word-wise fashion with the Command Register Reset
Command and a special masking algorithm.
Take for example the case of two-device (parallel) erasure.
The CPU first writes the data word erase command 2020H
twice in succession. This starts erasure. After 10ms, the CPU
writes the data word verify command A0A0H to stop erasure
and setup erase verification. If both one or both bytes are not
erased at the given address, the CPU implements the erase
sequence again without incrementing the address.
Suppose at the given address only the low byte verifies FFH
data Could the whole chip be erased The answer is yes.
Rather than check the rest of the low byte addresses
independently of the high byte, simply use the reset
command to mask the low byte from erasure and erase
verification on the next erase loop. In this example the erase
command would be 20FFH and the verify command would
be A0FFH. Once the high byte verifies at the address, the
CPU modifies the command back to the default 2020H and
A0A0H, increments to the next address, and then writes the
verify command.
See Figure 4 for a conceptual view of the parallel erase flow
chart and Figure 4 for the detailed version. These flow charts
are for the 16-bit systems and can be expanded for 32-bit
designs.
ERASE VERIFY:
The erase operation erases all locations in the device selected
in parallel. Upon completion of the erase operation, each
location must be verified. This operation is initiated by writing
A0H
to the command register. The address to be verified
must be supplied in order to be latched on the falling edge of
WE.
30A072-11
REV. A
2
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