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參數(shù)資料
| 型號(hào)： | DPZ256X16IY3-12M |
| 英文描述： | x16 Flash EEPROM Module |
| 中文描述： | x16閃存EEPROM模塊 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 992K |
| 代理商： | DPZ256X16IY3-12M |
Dense-Pac Microsystems, Inc.
DPZ256X32IV3
PROGRAMMING CYCLE
9
ADDRESS
CE
OE
WE
DATA I/O
5.0V
V
DD
0V
V
PPH
V
PP
V
PPL
Alternative
Write Timing
CE
WE
NOTES:
1. Each SLCC contains two FLASH memory devices enabled by a
common chip enable. Typically this module would be used as a
x32 device with CE0 and CE1 tied together. When writing
commands to the Command Register under these conditions, the
command shown in the Command Definition Table should be
duplicated to each byte (I/O0 - I/O7, I/O8 - I/O15, I/O16 - I/O23,
I/O24 - I/O31) of the module. If the command to be written is
404040H like that for Setup Program/Program, 4040H would be
written to the module followed by the 32 bit data. A single device
can be programmed or erased by writing the appropriate command
to the device the operation is to be performed on while 00H is
written to the other devices that are enabled at the same time.
Care must be taken when doing Program Verify on a single device.
Make certain that no other devices are driving the data bus of the
devices that are not being verified but are enabled along with the
device that is being verified. Any device that is enabled during
Program Verify will be driving the data bus with the data that is
programmed at that address.
2. All voltages are with respect to V
SS
.
3. -2.0V min. for pulse width less than 20ns (V
IL
min. = -0.5V at DC
level).
4. Maximum DC voltage on V
PP
or A9 may over shoot to +14.0V for
periods less than 20ns.
5. Output shorted for no more than 1 second. No more than one
output shorted at a time.
6. Stresses greater than those under
ABSOLUTE MAXIMUM
RATINGS
may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
7. This parameter is guaranteed and not 100% tested.
8. Transition is measured at the point of
±
500mV from steady state
voltage.
9. Chip Enable Controlled Writes: Write operations are driven by
the valid combination of Chip Enable and Write Enable. In systems
where Chip Enable defines the write pulse width
(within a longer
Write Enable timing waveform)
all Set-up, Hold, and inactive Write
Enable times should be measured relative to the Chip Enable
waveform.
30A072-11
REV. A
7
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