1 of 6
111799
FEATURES
All-silicon time delay
3 independent buffered delays
Delay tolerance ±2ns for -10 through –60
Stable and precise over temperature and
voltage range
Leading and trailing edge accuracy
Economical
Auto-insertable, low profile
Standard 14-pin DIP, 8-pin DIP, or 16-pin
SOIC
Low-power CMOS
TTL/CMOS-compatible
Vapor phase, IR and wave solderable
Custom delays available
Quick turn prototypes
Extended temperature ranges available
PIN ASSIGNMENT
PIN DESCRIPTION
IN 1, IN 2, IN 3
- Inputs
OUT 1, OUT 2, OUT 3 - Outputs
GND
- Ground
VCC
- +5 Volts
NC
- No Connection
DESCRIPTION
The DS1013 series of delay lines has three independent logic buffered delays in a single package. The
devices are offered in a standard 14-pin DIP which is pin-compatible with hybrid delay lines. Alternative
8-pin DIP and surface mount packages are available which save PC board area. Since the DS1013
products are an all silicon solution, better economy is achieved when compared to older methods using
hybrid techniques. The DS1013 series delay lines provide a nominal accuracy of
±2ns for delay times
ranging from 10 ns to 60 ns, increasing to 5% for delays of 150 ns and longer. The DS1013 delay line
reproduces the input logic state at the output after a fixed delay as specified by the dash number extension
of the part number. The DS1013 is designed to reproduce both leading and trailing edges with equal
precision. Each output is capable of driving up to 10 74LS loads. Dallas Semiconductor can customize
standard products to meet special needs. For special requests and rapid delivery, call (972) 371–4348.
DS1013
3-in-1 Silicon Delay Line
www.dalsemi.com
IN 1
IN 2
IN 3
GND
VCC
OUT 1
OUT 2
OUT 3
1
2
3
4
6
5
8
7
DS1013M 8-pin DIP (300-mil)
See Mech. Drawings Section
DS1013S 16-pin SOIC
(300-mil)
See Mech. Drawings Section
IN 1
NC
IN 2
IN 3
NC
GND
NC
OUT 3
OUT 2
OUT 1
VCC
NC
1
2
3
4
5
6
7
16
15
14
13
12
8
9
10
11
IN 1
NC
IN 2
NC
IN 3
GND
NC
OUT 3
OUT 2
OUT 1
VCC
1
2
3
4
5
6
7
14
13
12
11
10
8
DS1013 14-pin DIP (300-mil)
See Mech. Drawings Section
9