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參數(shù)資料
| 型號： | DS1020-25 |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 8/9頁 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 256TAP 16-DIP |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 標(biāo)片/步級數(shù)： | 256 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 10ns |
| 接頭增量： | 0.25ns |
| 可用的總延遲： | 73.75ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 16-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 16-PDIP |
| 包裝： | 管件 |
DS1020
8 of 9
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of the output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of the output pulse.
TIMING DIAGRAM: NON-LATCHED PARALLEL MODE (S = 1, E = 1) Figure 6
TIMING DIAGRAM: LATCHED PARALLEL MODE (S=1) Figure 7
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1020-50 | 功能描述:延遲線/計(jì)時元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS10-20B | 制造商:TRANSMISSION DEVELOPMENTS 功能描述:MOULDED SPUR GEAR 1.0, 20 |
| DS1020G-025 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Delay Line |
| DS1020G-050 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Delay Line |
| DS1020G-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Delay Line |
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