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參數(shù)資料

型號(hào)：	DS1023S-25
廠商：	Maxim Integrated Products
文件頁(yè)數(shù)：	10/16頁(yè)
文件大?。?/td>	0K
描述：	IC DELAY LINE 256TAP 16-SOIC
產(chǎn)品培訓(xùn)模塊：	Lead (SnPb) Finish for COTS Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝：	45
標(biāo)片/步級(jí)數(shù)：	256
功能：	單發(fā)射，可編程
延遲到第一抽頭：	16.5ns
接頭增量：	0.25ns
可用的總延遲：	63.75ns
獨(dú)立延遲數(shù)：	1
電源電壓：	4.75 V ~ 5.25 V
工作溫度：	0°C ~ 70°C
安裝類型：	表面貼裝
封裝/外殼：	16-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝：	16-SOIC W
包裝：	管件
其它名稱：	DS1023S25

DS1023

3 of 16

Applications can read the setting of the DS1023 Delay Line by connecting the serial output pin (Q) to the

serial input (D) through a resistor with a value of 1 to 10 kohms (Figure 2). Since the read process is

destructive, the resistor restores the value read and provides isolation when writing to the device. The

resistor must connect the serial output (Q) of the last device to the serial input (D) of the first device of a

daisy chain (Figure 1). For serial readout with automatic restoration through a resistor, the device used to

write serial data must go to a high impedance state.

To initiate a serial read, latch enable (LE) is taken to a logic 1 while serial clock (CLK) is at a logic 0.

After a waiting time (tEQV), bit 7 (MSB) appears on the serial output (Q). On the first rising (0 --> 1)

transition of the serial clock (CLK), bit 7 (MSB) is rewritten and bit 6 appears on the output after a time

tCQV. To restore the input register to its original state, this clocking process must be repeated eight times.

In the case of a daisy chain, the process must be repeated eight times per package. If the value read is

restored before latch enable (LE) is returned to logic 0, no settling time (tEDV) is required and the

programmed delay remains unchanged.

Since the DS1023 is a CMOS design, unused input pins (P3 - P7) must be connected to well-defined logic

levels; they must not be allowed to float. Serial output Q/P0 should be allowed to float if unused.

CASCADING MULTIPLE DEVICES (DAISY CHAIN) Figure 1

SERIAL READOUT Figure 2

REFERENCE DELAY

In all delay lines there is an inherent, or “step zero”, delay caused by the propagation delay through the

input and output buffers. In this device the step zero delay can be quite large compared to the delay step

size. To simplify system design a reference delay has been included on chip which may be used to

compensate for the step zero delay. In practice this means that if the device is supplied with a clock, for

example, the minimum programmed output delay is effectively zero with respect to the reference delay.

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
DS1023S-25/T&R	制造商:Maxim Integrated Products 功能描述:PROG 8-BIT DELAY 0.25NS SOIC T/R - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC DEL LN 256TAP 63.75NS 16SOIC 制造商:Maxim Integrated Products 功能描述:Delay Lines / Timing Elements Programmable 8-Bit .25ns Timing Element
DS1023S-25/T&R	功能描述:延遲線/計(jì)時(shí)元素 Programmable 8-Bit .25ns Timing Element RoHS:否制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube
DS1023S-25+	功能描述:延遲線/計(jì)時(shí)元素 Programmable 8-Bit .25ns Timing Element RoHS:否制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube
DS1023S-25+T	功能描述:延遲線/計(jì)時(shí)元素 Programmable 8-Bit .25ns Timing Element RoHS:否制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube
DS1023S-25+W	功能描述:延遲線/計(jì)時(shí)元素 Programmable 8-Bit .25ns Timing Element RoHS:否制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube

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