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參數(shù)資料
| 型號： | DS1023S-50+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 256TAP 16-SOIC |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1,000 |
| 標片/步級數(shù)： | 256 |
| 功能： | 單發(fā)射，可編程 |
| 延遲到第一抽頭： | 16.5ns |
| 接頭增量： | 0.5ns |
| 可用的總延遲： | 127.5ns |
| 獨立延遲數(shù)： | 1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
DS1023
9 of 16
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin
-1.0V to +7.0V
Operating Temperature Range
0
°C to 70°C
Storage Temperature
-55
°C to +125°C
Soldering Temperature
260
°C for 10 seconds
Short Circuit Output Current
50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 5V ± 5%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Supply Voltage
VCC
4.75
5
5.25
V
High Level Input Voltage
VIH
2
VCC +0.5
V
Low Level Input Voltage
VIL
-0.5
0.8
V
Input Leakage Current
(0<VI <VCC )
II
-1
+1
A
Active Current
ICC
30
60
mA
High Level Output Current
(VCC = Min, VOH = 2.7V)
IOH
-1
mA
Low Level Output Current
(VCC = Min, VOL = 0.5V)
-Q output
-
All other outputs
IOL
4
8
mA
AC ELECTRICAL CHARACTERISTICS - CONTROL/INTERFACE
SPECIFICATIONS ALL SPEED OPTIONS
(TA= 0
°C to 70°C; VCC= 5V ± 5%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Serial Clock Frequency
fCLK
10
MHz
Input Pulse Width (LE, CLK)
tW
50
ns
Data Setup to Clock
tDSC
30
ns
Data Hold from Clock
tDHC
0
ns
Data Setup to Enable
tDSE
30
ns
Data Hold from Enable
tDHE
0
ns
Enable Setup to Clock
tES
0
ns
Enable Hold from Clock
tEH
30
ns
LE to Q Valid
tEQV
50
ns
LE to Q Hi-Z
tEQZ
0
50
ns
CLK to Q Valid
tCQV
50
ns
CLK to Q Invalid
tCQX
0
ns
Parallel Input to Delay Valid
tPDV
500
ns
Parallel Input to Delay Invalid
tPDX
0
ns
LE to Delay Valid
tEDV
500
ns
LE to Delay Invalid
tEDX
0
ns
Power Up Time
tPU
100
ms
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