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參數(shù)資料
| 型號： | DS1050Z-025+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 17/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PWM 5BIT 25KHZ 2-WIRE 8SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 脈寬調(diào)制器（PWM） |
| PLL： | 無 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 25kHz |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC（窄型） |
| 包裝： | 帶卷 (TR) |
DS1050
9 of 17
NOTES:
1.
All voltages are referenced to ground.
2.
ICC specified with outputs open.
3.
I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VCC is switched off.
4.
Address Inputs, A0, A1, and A2, should be tied to either VCC or GND depending on the desired
address selections.
5.
ISTBY specified for VCC between 3.0V and 5.0V, control port logic pins are driven to the appropriate
logic levels.
6.
A fast mode device can be used in a standard mode system, but the requirement
tSU:DAT > 250ns must then be met. This will automatically be the case if the device does not stretch
the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000 + 250=1250ns before the SCL
line is released.
7.
After this period, the first clock pulse is generated.
8.
The maximum tSU:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the
SCL signal.
9.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the
VIH MIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
10. CB – total capacitance of one bus line in picofarads, timing referenced to (0.9)(VCC) and (0.1)(VCC).
11. A PWM output duty cycle change will occur with 2 periods of the output frequency when a change is
initiated.
12. The absolute frequency output of the PWM can be expected to fall within a
±20% range from the
nominal specified value of the device.
13. The DS1050 is a 5-bit PWM. The output duty cycles of the device range from 0% to 100% in step
sizes of 3.125%. The “Set PWM Duty Cycle 100%” allows the PWM output to be set to full-on.
14. Absolute Linearity is used to compare measured duty cycle against expected duty cycle as
determined by the DAC setting. The DS1050 is specified to provide an absolute linearity of
±0.5
LSB.
15. Relative Linearity is used to determine the change in duty cycle between adjacent or successive duty
cycle settings. The DS1050 is specified to provide a relative linearity specification of
±0.25 LSB.
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| DS1050Z-05 | 功能描述:IC PWM 5BIT 5KHZ 2-WIRE 8SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| DS1050Z-1/T&R | 制造商:Maxim Integrated Products 功能描述:IC CLK PWM 1KHZ 1CIRC 8SOIC |
| DS1050Z-1/T&R | 功能描述:IC PWM 5-BIT 1KHZ 2-WIRE 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| DS1050Z-10/T&R | 制造商:Maxim Integrated Products 功能描述:IC PWM 5-BIT 10KHZ 2-WIRE 8-SOIC |
| DS1050Z-10/T&R | 功能描述:IC PWM 5-BIT 10KHZ 2-WIRE 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
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