參數(shù)資料
型號: DS1086LU-21D+T
廠商: Maxim Integrated Products
文件頁數(shù): 5/17頁
文件大?。?/td> 0K
描述: IC ECONOSCILLATOR SS 8-USOP
其它有關(guān)文件: Automotive Product Guide
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 3,000
系列: EconOscillator™
類型: 擴(kuò)展頻譜時鐘發(fā)生器
PLL:
輸入: 時鐘
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 2:1
差分 - 輸入:輸出: 無/無
除法器/乘法器: 是/無
電源電壓: 2.7 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-uMAX
包裝: 帶卷 (TR)
3.3V Spread-Spectrum EconOscillator
Maxim Integrated
13
DS1086L
The expected output frequency is not exactly equal to the
desired frequency of 11.0592MHz. The difference is
450Hz. In terms of percentage, Equation 6 shows that the
expected error is 0.004%. The expected error assumes
typical values and does not include deviations from the
typical as specified in the electrical tables.
Example #2:
Calculate the register values needed to
generate a desired output frequency of 50MHz.
Since the desired frequency is already within the valid
master oscillator frequency range, the prescaler is set
to divide by 1, and hence, PRESCALER = 0000h
(currently ignoring the other setting).
fMASTER OSCILLATOR = 50.0MHz x 20 = 50.0MHz
Next, looking at Table 2, OS + 1 provides a range of
frequencies centered around the desired frequency. To
determine what value to write to the OFFSET register,
the RANGE register must first be read. Assuming 12h
was read in this example, 13h (OS + 1) is written to the
OFFSET register.
Finally, the DAC value is calculated as shown in
Equation 8.
The result is then converted to hex (0118h) and then
left-shifted, resulting in 4600h to be programmed into
the DAC register.
In summary, the DS1086L is programmed as follows:
PRESCALER = 0000h
OFFSET = OS + 1 or 13h (if RANGE was read as 12h)
DAC = 4600h
Since the expected output frequency is equal to the
desired frequency, the calculated error is 0%.
f
MHz
kHz
OUTPUT
(.
)
(
)
.
=
=
48 6
280
5
2
50 0
0
M
MHz
1
50 0
.
=
DAC VALUE
MHz
kHz STEP SI
(.
.
)
=
50 0
48 6
5
Z
ZE
decimal
.(
)
= 280 00
%ERROR
ff
f
EXPECTED
DESIRED
EXPECTED
DESIR
=
E
ED
EXPECTED
ERROR
MHz
%
..
×
=
100
11 0592
11 05
5875
11 0592
100
450
11 0592
MHz
Hz
MHz
.
×
.%
100
0 004
=
STOP
CONDITION
OR REPEATED
START
CONDITION
REPEATED IF MORE BYTES
ARE TRANSFERRED
ACK
START
CONDITION
ACK
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SLAVE ADDRESS
MSB
SCL
SDA
R/W
DIRECTION
BIT
12
6
7
8
9
12
8
9
3–7
Figure 4. 2-Wire Data Transfer Protocol
(6)
(7)
(8)
(9)
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