參數(shù)資料
型號: DS1086U-266+
廠商: Maxim Integrated Products
文件頁數(shù): 11/15頁
文件大小: 0K
描述: IC ECONOSCILLATOR SS 8-USOP
其它有關(guān)文件: Automotive Product Guide
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 50
系列: EconOscillator™
類型: 擴展頻譜時鐘發(fā)生器
PLL:
輸入: 時鐘
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 2:1
差分 - 輸入:輸出: 無/無
頻率 - 最大: 66MHz
除法器/乘法器: 是/無
電源電壓: 4.75 V ~ 5.25 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-uMAX
包裝: 管件
產(chǎn)品目錄頁面: 1436 (CN2011-ZH PDF)
DS1086
Spread-Spectrum EconOscillator
_______________________________________________________________________________________
5
AC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE (continued)
(VCC = 5V ±5%, TA = 0°C to +70°C.)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Fast mode
0.6
Setup Time for STOP
tSU:STO
Standard mode
4.0
s
Capacitive Load for Each Bus
Line
CB
(Note 16)
400
pF
NV Write-Cycle Time
tWR
10
ms
Input Capacitance
CI
5pF
Note 1:
All voltages are referenced to ground.
Note 2:
DAC and OFFSET register settings must be configured to maintain the master oscillator frequency within this range.
Correct operation of the device is not guaranteed if these limits are exceeded.
Note 3:
This is the absolute accuracy of the master oscillator frequency at the default settings.
Note 4:
This is the change that is observed in master oscillator frequency with changes in voltage from nominal voltage at
TA = +25°C.
Note 5:
This is the percentage frequency change from the +25°C frequency due to temperature at VCC = 5V. The maximum tem-
perature change varies with the master oscillator frequency setting. The minimum occurs at the default master oscillator
frequency (fdefault). The maximum occurs at the extremes of the master oscillator frequency range (66MHz or 133MHz)
(see Figure 2).
Note 6:
The dither deviation of the master oscillator frequency is unidirectional and lower than the undithered frequency.
Note 7:
The integral nonlinearity of the frequency adjust DAC is a measure of the deviation from a straight line drawn between the
two endpoints of a range. The error is in percentage of the span.
Note 8:
This is true when the prescaler = 1.
Note 9:
Frequency settles faster for small changes in value. During a change, the frequency transitions smoothly from the original
value to the new value.
Note 10:
This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally
introduced to allow the oscillator to stabilize. tstab is equivalent to approximately 512 master clock cycles and therefore
depends on the programmed clock frequency.
Note 11:
Output voltage swings can be impaired at high frequencies combined with high output loading.
Note 12:
A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met.
This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line at least tR MAX + tSU:DAT =
1000ns + 250ns = 1250ns before the SCL line is released.
Note 13:
After this period, the first clock pulse is generated.
Note 14:
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIH MIN of the SCL sig-
nal) in order to bridge the undefined region of the falling edge of SCL.
Note 15:
The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 16:
CB—total capacitance of one bus line, timing referenced to 0.9 x VCC and 0.1 x VCC.
Note 17:
Typical frequency shift due to aging is ±0.5%. Aging stressing includes Level 1 moisture reflow preconditioning (24hr
+125°C bake, 168hr 85°C/85%RH moisture soak, and 3 solder reflow passes +240 +0/-5°C peak) followed by 1000hr
max VCC biased 125°C HTOL, 1000 temperature cycles at -55°C to +125°C, 96hr 130°C/85%RH/5.5V HAST and 168hr
121°C/2 ATM Steam/Unbiased Autoclave.
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