參數(shù)資料
型號: DS1091LUA-10A/V+
廠商: Maxim Integrated Products
文件頁數(shù): 6/9頁
文件大?。?/td> 0K
描述: IC ECONOSCILLATOR SS 8UMAX
其它有關(guān)文件: Automotive Product Guide
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 50
系列: EconOscillator™
類型: 擴展頻譜時鐘發(fā)生器
PLL:
輸入: 時鐘
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 無/無
頻率 - 最大: 10.38MHz
除法器/乘法器: 是/無
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-uMAX
包裝: 管件
其它名稱: 90-1L91U+V03
DS1091L
Automotive Temperature Range
Spread-Spectrum EconOscillator
6
Maxim Integrated
Detailed Description
The DS1091L clock generator is capable of output fre-
quencies from 130kHz to 66.6MHz over the full automo-
tive temperature range (-40°C to +125°C). The device
can also produce a spread-spectrum (dithered) square-
wave output using four pin-selectable dither percent-
ages. Both center (DS1091LUA) and down (DS1091LUB)
dithering options are available. The device also features
two selectable dither rates.
The DS1091L is shipped from the factory programmed to
a customer-specified frequency.
Spread Spectrum
The DS1091L can reduce radiated emission peaks. The
dither percentage is controlled by the state of the SEL0
and SEL1 pins. The output frequency can be dithered
at 0%, ±1%, ±2%, and ±4%, centered around the pro-
grammed frequency (for the DS1091LUB this can be
down dithered by 0%, -2%, -4%, and -8%).
The two select pins SEL0 and SEL1 provide a means of
selecting the dither magnitudes as follows:
A triangle-wave generator injects a control signal into the
master oscillator to dither its output. The dither rate is a
function of the output frequency, fOUT, as well as the set-
ting of the DR pin (see the equation below). Figure 1A and
Figure 1B show a plot of the output frequency vs. time.
OUT
n
f
DITHER RATE
2
=
where n is defined in Table 2 as a function of output
frequency. For example, for an output frequency of
27.0MHz, the dither rate would be 13.2kHz for DR = 1
and 6.6kHz for DR = 0.
Power-Up
Upon the application of power, the DS1091L output is
held in the low state until tPU has elapsed. This removes
any possibility of erroneous output transitions during ini-
tial power-up.
DS1091L Frequency Spreading Profile as a Function of Dither %
Figure 1A. Center Dithered
Figure 1B. Down Dithered
Table 1. Dither Magnitude
Table 2. Value of n w.r.t. Output Frequency
SEL1
LOGIC
LEVEL
SEL0
LOGIC
LEVEL
DITHER MAGNITUDE (%)
DS1091LUA
DS1091LUB
0
No dither
0
1
Q
1
-2
1
0
Q
2
-4
1
Q
4
-8
OUTPUT FREQUENCY fOUT
(MHz)
n
fOUT (min)
fOUT (max)
DR = LOGIC
LEVEL 1
DR = LOGIC
LEVEL 0
0.130
0.260
4
5
0.261
0.521
5
6
0.522
1.042
6
7
1.043
2.083
7
8
2.084
4.167
8
9
4.168
8.333
9
10
8.334
16.667
10
11
16.668
33.333
11
12
33.334
66.667
12
13
TIME
1
DITHER FREQ
PROGRAMMED fOUT+
(1%, 2%, OR 4% OF fOUT)
PROGRAMMED fOUT-
(1%, 2%, OR 4% OF fOUT)
PROGRAMMED fOUT
DITHER
AMOUNT
(±1%, ±2%,
OR ±4%)
IF DITHER AMOUNT = 0%
f OUT
TIME
1
DITHER FREQ
PROGRAMMED fOUT
PROGRAMMED fOUT-
(2%, 4%, OR 8% OF fOUT)
DITHER
AMOUNT
(-2%, -4%,
OR -8%)
IF DITHER AMOUNT = 0%
f OUT
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