參數(shù)資料
型號(hào): DS1100U-50+
廠商: Maxim Integrated Products
文件頁數(shù): 3/7頁
文件大?。?/td> 0K
描述: IC DELAY LINE 5TAP 50NS 8-USOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 50
標(biāo)片/步級(jí)數(shù): 5
功能: 不可編程
延遲到第一抽頭: 10ns
接頭增量: 10ns
可用的總延遲: 50ns
獨(dú)立延遲數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-uMAX
包裝: 管件
DS1100
3 of 7
NOTES:
1) Initial tolerances are ± with respect to the nominal value at +25°C and 5V for both leading and
trailing edge.
2) Temperature and voltage tolerance is with respect to the nominal delay value over the stated
temperature range, and a supply-voltage range of 4.75V to 5.25V.
3) All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if
TAP1 slows down, all other taps also slow down; TAP3 can never be faster than TAP2.
4) Intermediate delay values are available on a custom basis. For further information, email the factory
5) All voltages are referenced to ground.
6) Measured with outputs open.
7) See Test Conditions section at the end of this data sheet.
8) Frequencies higher than 1MHz result in higher ICC values.
9) At or near maximum frequency the delay accuracy can vary and will be application sensitive (i.e.,
decoupling, layout).
Figure 1. LOGIC DIAGRAM
Figure 2. TIMING DIAGRAM: SILICON DELAY LINE
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DS1100U-50+T&R 制造商:Maxim Integrated Products 功能描述:ACTV TAPPED DLY LINE 5 TAP 1-IN 10NS ABS 50NS MAX 8USOP - Tape and Reel
DS1100U-500 功能描述:延遲線/計(jì)時(shí)元素 5-Tap Timing Element RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube
DS1100U-500+ 功能描述:延遲線/計(jì)時(shí)元素 5-Tap Timing Element RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube