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參數(shù)資料
| 型號： | DS1135LZ-30+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/7頁 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 30NS 8-SOIC |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 功能： | 多個，不可編程 |
| 延遲到第一抽頭： | 30ns |
| 可用的總延遲： | 30ns |
| 獨立延遲數(shù)： | 3 |
| 電源電壓： | 2.7 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
DS1135L
6 of 7
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI(Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge on the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of the output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the falling edge of the input
pulse and the 1.5V point on the falling edge of the output pulse.
ORDERING INFORMATION
PACKAGE INFORMATION
For
the
latest
package
outline
information
and
land
patterns
(footprints),
go
to
www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of
RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
8 SO
S8+2
DS1135L
PACKAGE TYPE:
Z = SO (150MIL)
Dash
Delay (NS)
Number
Time
10
12
15
20
25
30
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| DS1135M-25 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3-in-1 High-Speed Silicon Delay Line |
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