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參數(shù)資料
| 型號： | DS1135U-8+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 8NS 8-USOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 功能： | 多個(gè)，不可編程 |
| 延遲到第一抽頭： | 8ns |
| 可用的總延遲： | 8ns |
| 獨(dú)立延遲數(shù)： | 3 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
DS1135
5 of 7
TEST CONDITIONS
Ambient Temperature: 25°C ± 3°C
Supply Voltage (VCC): 5.0V ± 0.1V
Input Pulse:
High: 3.0V ± 0.1V
Low: 0.0V ± 0.1V
Source Impedance: 50 Max.
Rise and Fall Time: 3.0ns Max. - Measured between 0.6V and 2.4V.
Pulse Width: 500ns
Pulse Period: 1s
Output Load Capacitance: 15pF
Output: Each output is loaded with the equivalent of one 74F04 input gate.
Data is measured at the 1.5V level on the rising and falling edges.
Note: The above conditions are for test only and do not restrict the devices under other data sheet
conditions.
NOTES:
1. All voltages are referenced to ground.
2. Pulse width and duty cycle specifications may be exceeded; however, accuracy will be application
sensitive with respect to decoupling, layout, etc.
3. Power-up time is the time from the application of power to the time stable delays are being produced
at the output.
TIMING DIAGRAM
tFALL
80%
tRISE
20%
IN
OUT
1.5V
tWI
PERIOD
1.5V
tPLH
tPHL
tOF
tOR
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