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參數(shù)資料
| 型號(hào)： | DS1222S+ |
| 廠商： | Maxim Integrated |
| 文件頁(yè)數(shù)： | 2/4頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC BANKSWITCH CMOS 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 45 |
| 控制器類型： | 靜態(tài) RAM（SRAM） |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 管件 |
DS1222
2 of 4
OPERATION - BANK SWITCHING
Initially, on power-up all four bank select outputs are low and the chip enable output ( CEO ) is held high.
(Note: the power fail input [
I
F
P
] must be low prior to power-up to assure proper initialization.) Bank
switching is achieved by matching a predefined pattern stored within the DS1222 with a 16-bit sequence
received on four address inputs. Prior to entering the 16-bit pattern, which sets the bank switch, a read
cycle of 1111 on address inputs AW through AZ should be executed to guarantee that pattern entry starts
with bit 0. Each set of address inputs is clocked into the DS1222 when CEI is driven low. All 16 inputs
must be consecutive read cycles. The first eleven cycles must match the exact bit pattern as shown in
Table 1. The last five cycles must match the exact bit pattern as shown for addresses AX, AY, and AZ.
However, address line AW defines the bank number to be enabled as per Table 2.
Switching to a selected bank of memory occurs on the rising edge of CEI when the last set of bits is input
and a match has been established. After bank selection CEO always follows CEI with a maximum
propagation delay of 15 ns. The bank selected is determined by the levels set on Bank Select 1 through
Bank Select 4 as per Table 2. These levels are held constant for all memory cycles until a new memory
bank is selected.
ADDRESS BIT SEQUENCE Table 1
BIT SEQUENCE
ADDRESS
INPUTS
0123456789
10
11
12
13
14
15
AW
10100011010
xxxxx
AX
0101110010100011
AY
1010001101011100
AZ
0101110010100011
X See Table 2
BANK SELECT CONTROL Table 2
AW Bit Sequence
Outputs
Bank
Selected
11
12
13
14
15
BS1
BS2
BS3
BS4
*Banks Off
0
XX
Low
Bank 0
1
00
Low
Bank 1
1
00
01
High
Low
Bank 2
1
00
10
Low
High
Low
Bank 3
1
00
11
High
Low
Bank 4
1
01
00
Low
High
Low
Bank 5
1
01
High
Low
High
Low
Bank 6
1
01
10
Low
High
Low
Bank 7
1
0
1
High
Low
Bank 8
1
10
00
Low
High
Bank 9
1
10
01
High
Low
High
Bank 10
11
01
0
Low
High
Low
High
Bank 11
11
01
1
High
Low
High
Bank 12
11
10
0
Low
High
Bank 13
1
0
1
High
Low
High
Bank 14
1
0
Low
High
Bank 15
1
High
* CEO =VIH independent of CEI
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1222S+ | 功能描述:IC BANKSWITCH CMOS 16-SOIC RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 控制器類型:靜態(tài) RAM（SRAM） 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC W 包裝:管件 |
| DS1222SN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| DS1223 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ELECTRONIC CONFIGURATOR|CMOS|DIP|24PIN|PLASTIC |
| DS1225 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:64K Nonvolatile SRAM |
| DS1225AB | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:64k Nonvolatile SRAM |
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