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  • 參數(shù)資料
    型號: DS1244Y-120
    英文描述: 256K NV SRAM with Phantom Clock
    中文描述: 256K非易失SRAM與幻影時鐘
    文件頁數(shù): 7/12頁
    文件大?。?/td> 100K
    代理商: DS1244Y-120
    DS1244Y
    032697 4/12
    PHANTOM CLOCK REGISTER DEFINITION Figure 2
    76
    54
    3
    2
    1
    0
    0.1 SEC
    00–99
    00–59
    01–12
    01–07
    01–31
    01–12
    00–99
    0
    1
    2
    3
    4
    5
    6
    7
    RANGE
    (BCD)
    REGISTER
    0
    12/24
    0
    10
    HR
    00
    0
    00
    0
    10
    MONTH
    10 YEAR
    YEAR
    0.01 SEC
    00–23
    10 SEC
    SECONDS
    10 MIN
    MINUTES
    A/P
    HOUR
    OSC
    RST
    DAY
    10 DATE
    DATE
    MONTH
    AM–PM/12/24 MODE
    Bit 7 of the hours register is defined as the 12– or
    24–hour mode select bit. When high, the 12–hour mode
    is selected. In the 12–hour mode, bit 5 is the AM/PM bit
    with logic high being PM. In the 24–hour mode, bit 5 is
    the second 10–hour bit (20–23 hours).
    OSCILLATOR AND RESET BITS
    Bits 4 and 5 of the day register are used to control the
    RESET and oscillator functions.
    Bit 4 controls the
    RESET (pin 1). When the RESET bit is set to logic 1, the
    RESET input pin is ignored. When the RESET bit is set
    to logic 0, a low input on the RESET pin will cause the
    Phantom Clock to abort data transfer without changing
    data in the watch registers. Bit 5 controls the oscillator.
    When set to logic 1, the oscillator is off. When set to log-
    ic 0, the oscillator turns on and the watch becomes op-
    erational. These bits are shipped from the factory set to
    a logic 1.
    ZERO BITS
    Registers 1, 2, 3, 4, 5, and 6 contain one or more bits
    which will always read logic 0. When writing these loca-
    tions, either a logic 1 or 0 is acceptable.
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    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
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