參數(shù)資料
型號(hào): DS1248W-120IND
廠商: Maxim Integrated Products
文件頁數(shù): 14/19頁
文件大?。?/td> 0K
描述: IC NVSRAM 1MBIT 120NS 32DIP
標(biāo)準(zhǔn)包裝: 11
類型: Phantom 計(jì)時(shí)芯片
特點(diǎn): NVSRAM
存儲(chǔ)容量: 128KB
時(shí)間格式: HH:MM:SS:hh(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: 并聯(lián)
電源電壓: 2.97 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 32-DIP 模塊(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 32-EDIP
包裝: 管件
DS1248/DS1248P 1024K NV SRAM with Phantom Clock
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RAM READ MODE
The DS1248 executes a read cycle whenever WE (write enable) is inactive (high) and CE (chip enable) is
active (low). The unique address specified by the 17 address inputs (A0–A16) defines which of the 128k
bytes of data is to be accessed. Valid data will be available to the eight data-output drivers within tACC
(access time) after the last address input signal is stable, providing that CE and OE (output enable) access
times and states are also satisfied. If OE and CE access times are not satisfied, then data access must be
measured from the later occurring signal (CE or OE) and the limiting parameter is either tCO for CE or tOE
for OE, rather than address access.
RAM WRITE MODE
The DS1248 is in the write mode whenever the WE and CE signals are in the active (low) state after
address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CEor WE. All address inputs must
be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output bus has been enabled (CE and OE active)
then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF.
However, when VCC is below the power-fail point, VPF (point at which write protection occurs), the
internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch
point, VSO (battery supply level), device power is switched from the VCC pin to the backup battery. RTC
operation and SRAM data are maintained from the battery until VCC is returned to nominal levels.
The 3.3V device is fully accessible and data can be written or read only when VCC is greater than VPF.
When VCC falls below VPF, access to the device is inhibited. If VPF is less than VBAT, the device power is
switched from VCC to the backup supply (VBAT) when VCC drops below VPF. If VPF is greater than VBAT,
the device power is switched from VCC to the backup supply (VBAT) when VCC drops below VBAT. RTC
operation and SRAM data are maintained from the battery until VCC is returned to nominal levels.
All control, data, and address signals must be powered down when VCC is powered-down.
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