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參數(shù)資料
| 型號(hào)： | DS1265W-150-IND |
| 英文描述： | 3.3V 8Mb Nonvolatile SRAM |
| 中文描述： | 3.3和8Mb非易失SRAM |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 155K |
| 代理商： | DS1265W-150-IND |
DS1265W
2 of 8
READ MODE
The DS1265 devices execute a read cycle whenever
WE
(Write Enable) is inactive (high) and
CE
(Chip
Enable) and
OE
(Output Enable) are active (low). The unique address specified by the 20 address inputs
(A
0
–A
19
) defines which of the 1,048,576 bytes of data is accessed. Valid data will be available to the
eight data output drivers within t
ACC
(Access Time) after the last address input signal is stable, providing
that
CE
and
OE
access times are also satisfied. If
OE
and
CE
access times are not satisfied, then data
access must be measured from the later-occurring signal (
CE
or
OE
) and the limiting parameter is either
t
CO
for
CE
or t
OE
for
OE
rather than t
ACC
.
WRITE MODE
The DS1265 devices execute a write cycle whenever
WE
and
CE
signals are active (low) after address
inputs are stable. The later-occurring falling edge of
CE
or
WE
will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of
CE
or
WE
. All address inputs must be kept
valid throughout the write cycle.
WE
must return to the high state for a minimum recovery time (t
WR
)
before another cycle can be initiated. The
OE
control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled (
CE
and
OE
active), then
WE
will disable the outputs in t
ODW
from its falling edge.
DATA-RETENTION MODE
The DS1265W provides full functional capability for V
CC
greater than 3.0V and write protects by 2.8V.
Data is maintained in the absence of V
CC
without any additional support circuitry. The nonvolatile static
RAMs constantly monitor V
CC
. Should the supply voltage decay, the NV SRAMs automatically write
protect themselves, all inputs become “don’t care,” and all outputs become high-impedance. As V
CC
falls
below approximately 2.5V, a power-switching circuit connects the lithium energy source to RAM to
retain data. During power-up, when V
CC
rises above approximately 2.5V, the power-switching circuit
connects external V
CC
to RAM and disconnects the lithium energy source. Normal RAM operation can
resume after V
CC
exceeds 3.0V.
FRESHNESS SEAL
Each DS1265 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When V
CC
is first applied at a level greater than V
TP
, the lithium
energy source is enabled for battery backup operation.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1265Y | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:8M Nonvolatile SRAM |
| DS1265Y/AB | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:8M Nonvolatile SRAM |
| DS1265Y-100 | 功能描述:NVRAM 8M NV SRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類(lèi)型:Parallel 訪問(wèn)時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1265Y-100+ | 功能描述:NVRAM 8M NV SRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類(lèi)型:Parallel 訪問(wèn)時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1265Y-100-IND | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:NVRAM (Battery Based) |
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