參數(shù)資料
型號: DS1302S-16/T&R
廠商: Maxim Integrated Products
文件頁數(shù): 9/13頁
文件大?。?/td> 0K
描述: IC TIMEKEEPER T-CHARGE 16-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1,000
類型: 時鐘/日歷
特點(diǎn): 閏年,NVSRAM,涓流充電器
存儲容量: 31B
時間格式: HH:MM:SS(12/24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: 3 線串口
電源電壓: 2 V ~ 5.5 V
電壓 - 電源,電池: 2 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC W
包裝: 帶卷 (TR)
DS1302 Trickle-Charge Timekeeping Chip
5 of 13
OSCILLATOR CIRCUIT
The DS1302 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or
capacitors to operate. Table 1 specifies several crystal parameters for the external crystal. Figure 1 shows a
functional schematic of the oscillator circuit. If using a crystal with the specified characteristics, the startup time is
usually less than one second.
CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between
the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional
error will be added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the
oscillator circuit may result in the clock running fast. Figure 2 shows a typical PC board layout for isolating the
crystal and oscillator from noise. Refer to
Application Note 58: Crystal Considerations for Dallas Real-Time Clocks
for detailed information.
Table 1. Crystal Specifications*
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Nominal Frequency
fO
32.768
kHz
Series Resistance
ESR
45
k
Ω
Load Capacitance
CL
6
pF
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to
Application Note 58: Crystal Considerations for Dallas Real-Time Clocks
for additional specifications.
Figure 2. Typical PC Board Layout for Crystal
LOCAL GROUND PLANE (LAYER 2)
CRYSTAL
X1
X2
GND
NOTE: AVOID ROUTING SIGNALS IN THE
CROSSHATCHED AREA (UPPER LEFT-
HAND QUADRANT) OF THE PACKAGE
UNLESS THERE IS A GROUND PLANE
BETWEEN THE SIGNAL LINE AND THE
PACKAGE.
COMMAND BYTE
Figure 3 shows the command byte. A command byte initiates each data transfer. The MSB (bit 7) must be a logic
1. If it is 0, writes to the DS1302 will be disabled. Bit 6 specifies clock/calendar data if logic 0 or RAM data if logic 1.
Bits 1 to 5 specify the designated registers to be input or output, and the LSB (bit 0) specifies a write operation
(input) if logic 0 or read operation (output) if logic 1. The command byte is always input starting with the LSB (bit 0).
Figure 3. Address/Command Byte
1
RAM
CK
A4
A3
A2
A1
A0
RD
WR
7654
3210
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