參數(shù)資料
型號(hào): DS1315EN-33/T&R
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 10/21頁(yè)
文件大小: 0K
描述: IC T-CHP PHANTOM 3.3V IN 20TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: Phantom 計(jì)時(shí)芯片
特點(diǎn): 閏年
時(shí)間格式: HH:MM:SS:hh(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: 并聯(lián)
電源電壓: 3 V ~ 3.6 V
電壓 - 電源,電池: 2.5 V ~ 3.7 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 帶卷 (TR)
DS1315 Phantom Time Chip
18 of 21
NOTES:
1) All voltages are referenced to ground.
2) Measured with load shown in Figure 15.
3) Input pulse rise and fall times equal 10ns.
4) tWR is a function of the latter occurring edge of WE or CE in RAM mode, or OE or CE in ROM
mode.
5) tDH and tDS are functions of the first occurring edge of WE or CE in RAM mode, or OE or CE in
ROM mode.
6) Measured without RAM connected.
7) ICCO1 is the maximum average load current the DS1315 can supply to external memory.
8) Applies to CEO with the ROM/ RAM pin grounded. When the ROM/ RAM pin is connected to VCCO,
CEO
will go to a low level as VCCI falls below VBAT.
9) ICCO2 is the maximum average load current that the DS1315 can supply to memory in the battery
backup mode.
10) Applies to all input pins except RST . RST is pulled internally to VCCI.
11) See Figures 11 and 12.
12) See Figures 13 and 14.
13) VSW is determined by the larger of VBAT1 and VBAT2.
14) VSW is determined by the smaller of VBAT1, VBAT2, and VPF.
Figure 13. 3.3V Power-Up Condition
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