參數(shù)資料
型號: DS1318
元件分類: 通用總線功能
英文描述: Parallel-Interface Elapsed Time Counter
中文描述: 并行接口歷時計數(shù)器
文件頁數(shù): 11/14頁
文件大?。?/td> 158K
代理商: DS1318
Special-Purpose Registers
The DS1318 has three additional registers (control A,
control B, and status) that control the clock, alarms,
square wave, and interrupt output. The subseconds0
register has a square-wave synchronization (SQWS) bit
in the bit 0 location. Writing the SQWS bit to 1 clears
the square-wave prescaler and holds it in reset. Only
the frequencies below 4096Hz are reset. Writing the bit
back to 0 takes the prescaler out of reset and starts the
square wave running.
Bit 7: Transfer Enable (TE).
When TE is set to logic 1,
the DS1318 continues to update the user copy of the
time value as it receives 4,096Hz clock pulses from the
oscillator. To ensure reading valid time data from the
part, the user should set TE to logic 0 before reading
registers 00–05h. TE must be enabled (logic 1) for at
least 244μs to ensure that a transfer occurs. Note that
because of the 244μs restriction, sequential values of
the subseconds0 register cannot be read when TE
is used.
It is possible that TE could be set to logic 0 while a
transfer is taking place. In that case, the buffered data
could be invalid. To prevent this, the UIP bit, described
later, should be used. To write data to the clock regis-
ters, the user should set TE to logic 0, write the regis-
ters, and set TE to logic 1.
Bit 6: Enable Oscillator (ENOSC).
When ENOSC is set
to logic 1, the DS1318 crystal oscillator becomes
enabled. Actual startup time for the oscillator depends on
many external variables and is not a specified parameter.
Bits 5, 4: Clock Configuration 1, 0 (CCFG1, CCFG0).
These bits determine which of the four possible modes
the DS1318 uses to clock its timekeeping registers:
Bit 3: External Polarity (EPOL).
This bit controls the
polarity on the EXT pin input when the CCFG1 and
CCFG0 bits are equal to 0 and 1, respectively. When
EPOL is set to logic 1, the registers count when the EXT
pin is 1. When EPOL is set to logic 0, the registers
count when the EXT pin is logic 0.
Bit 2: Square-Wave Enable (SQWE).
When SQWE is
set to logic 1, a frequency determined by the SRSx bits
in control register B (0Bh) is output on the SQW pin.
When SQWE is logic 0, the SQW pin is always 0. When
the part is in power-fail, the SQW pin is always high-
impedance. The square-wave output uses a separate
prescaler from the one used by PF,
IRQ
, UIP, and the
up counter. The SQWS bit in control register A can be
used to synchronize the square-wave output to within
244μs of the other events.
Bit 1: Periodic Interrupt Enable (PIE).
When PIE is set
to logic 1, the DS1318 sets the
IRQ
pin low whenever
the PF flag is set to 1. When PIE is 0, the PF flag does
not affect the
IRQ
pin.
Bit 0: Alarm Interrupt Enable (AIE).
When AIE is set to
logic 1, the DS1318 sets the
IRQ
pin low whenever the
ALMF flag is set to 1. When AIE is 0, the ALMF flag
does not affect the
IRQ
pin.
D
Parallel-Interface Elapsed Time Counter
____________________________________________________________________
11
BIT 7
TE
BIT 6
ENOSC
BIT 5
CCFG1
BIT 4
CCFG0
BIT 3
EPOL
BIT 2
SQWE
BIT 1
PIE
BIT 0
AIE
Control Register A (0Ah)
CCFG1
0
CCFG0
0
MODE
Always clocks the registers (normal mode)
0
1
Clocks when the EXT pin is “active” and
V
CC
is greater than V
PF
(event-timer mode,
depends on EPOL bit)
1
0
Clocks registers when part is running on
V
CC
1
1
Clocks registers when part is running on
V
BAT
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