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參數(shù)資料
| 型號(hào)： | DS1330ABP-100-IND |
| 英文描述： | 256k Nonvolatile SRAM with Battery Monitor |
| 中文描述： | 256k非易失SRAM與電池監(jiān)視器 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大小： | 191K |
| 代理商： | DS1330ABP-100-IND |
DS1330Y/AB
7 of 11
POWER-DOWN/POWER-UP TIMING
(t
A
: See Note 10)
PARAMETER
SYMBOL
V
CC
Fail Detect to
CE
and
WE
Inactive
t
PD
V
CC
slew from V
TP
to 0V
t
F
t
RPD
V
CC
slew from 0V to V
TP
t
R
t
PU
V
CC
Valid to End of Write Protection
t
REC
V
CC
Valid to
RST
Inactive
t
RPU
V
CC
Valid to
BW
Valid
t
BPU
MIN
TYP
MAX
1.5
UNITS
NOTES
11
s
150
s
s
V
CC
Fail Detect to
RST
Active
15
14
150
s
V
CC
Valid to
CE
and
WE
Inactive
2
ms
125
350
ms
ms
150
200
14
1
s
14
BATTERY WARNING TIMING
(t
A
: See Note 10)
PARAMETER
SYMBOL
Battery Test Cycle
t
BTC
Battery Test Pulse Width
t
BTPW
Battery Test to
BW
Active
t
BW
MIN
TYP
24
MAX
UNITS
hr
s
s
NOTES
1
1
(t
A
= 25 C)
PARAMETER
SYMBOL
Expected Data Retention Time
t
DR
MIN
10
TYP
MAX
UNITS
years
NOTES
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1.
WE
is high for a Read Cycle.
2.
OE
= V
IH
or V
IL
. If
OE
= V
IH
during write cycle, the output buffers remain in a high-impedance state.
3.
t
WP
is specified as the logical AND of
CE
and
WE
. t
WP
is measured from the latter of
CE
or
WE
going low to the earlier of
CE
or
WE
going high.
4.
t
DS
is measured from the earlier of
CE
or
WE
going high.
5.
These parameters are sampled with a 5pF load and are not 100% tested.
6.
If the
CE
low transition occurs simultaneously with or latter than the
WE
low transition, the output
buffers remain in a high-impedance state during this period.
7.
If the
CE
high transition occurs prior to or simultaneously with the
WE
high transition, the output
buffers remain in high-impedance state during this period.
8.
If
WE
is low or the
WE
low transition occurs prior to or simultaneously with the
CE
low transition,
the output buffers remain in a high-impedance state during this period.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1330ABP-70 | 功能描述:NVRAM 256K NV RAM w/Battery Monitor RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1330ABP-70+ | 功能描述:NVRAM 256K NV RAM w/Battery Monitor RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1330ABP-70IND | 功能描述:NVRAM 256K NV RAM w/Battery Monitor RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1330ABP-70-IND | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:256k Nonvolatile SRAM with Battery Monitor |
| DS1330ABP-70IND+ | 功能描述:NVRAM 256K NV RAM w/Battery Monitor RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
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