2C Serial Real-Time Clock Table 3. Alarm Mask Bits ALARM 1 REGISTER MASK BITS (BIT 7) DY/DT A1" />
參數(shù)資料
型號: DS1337U
廠商: Maxim Integrated Products
文件頁數(shù): 2/16頁
文件大?。?/td> 0K
描述: IC RTC SERIAL 2WIRE LP 8-USOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 50
類型: 時鐘/日歷
特點: 警報器,閏年,方波輸出,涓流充電器
時間格式: HH:MM:SS(12/24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 1.8 V ~ 5.5 V
電壓 - 電源,電池: 1.3 V ~ 1.8 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-uMAX
包裝: 管件
DS1337 I
2C Serial Real-Time Clock
Table 3. Alarm Mask Bits
ALARM 1 REGISTER MASK BITS
(BIT 7)
DY/DT
A1M4
A1M3
A1M2
A1M1
ALARM RATE
X
1
Alarm once per second
X
1
0
Alarm when seconds match
X
1
0
Alarm when minutes and seconds match
X
1
0
Alarm when hours, minutes, and seconds match
0
Alarm when date, hours, minutes, and seconds
match
1
0
Alarm when day, hours, minutes, and seconds match
ALARM 2 REGISTER MASK BITS
(BIT 7)
DY/DT
A2M4
A2M3
A2M2
ALARM RATE
X
1
Alarm once per minute (00 seconds of every minute)
X
1
0
Alarm when minutes match
X
1
0
Alarm when hours and minutes match
0
Alarm when date, hours, and minutes match
1
0
Alarm when day, hours, and minutes match
SPECIAL-PURPOSE REGISTERS
The DS1337 has two additional registers (control and status) that control the RTC, alarms, and square-wave
output.
Control Register (0Eh)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EOSC
0
RS2
RS1
INTCN
A2IE
A1IE
Bit 7: Enable Oscillator (EOSC). This active-low bit when set to logic 0 starts the oscillator. When this bit is set to
logic 1, the oscillator is stopped. This bit is enabled (logic 0) when power is first applied.
Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the square-wave output when the
square wave has been enabled. The table below shows the square-wave frequencies that can be selected with the
RS bits. These bits are both set to logic 1 (32kHz) when power is first applied.
SQW/INTB Output
INTCN
RS2
RS1
SQW/INTB
OUTPUT
A2IE
0
1Hz
X
0
1
4.096kHz
X
0
1
0
8.192kHz
X
0
1
32.768kHz
X
1
X
A2F
1
Bit 2: Interrupt Control (INTCN). This bit controls the relationship between the two alarms and the interrupt output
pins. When the INTCN bit is set to logic 1, a match between the timekeeping registers and the alarm 1 registers l
activates the
INTA pin (provided that the alarm is enabled) and a match between the timekeeping registers and the
alarm 2 registers activates the SQW/
INTB pin (provided that the alarm is enabled). When the INTCN bit is set to
logic 0, a square wave is output on the SQW/
INTB pin. This bit is set to logic 0 when power is first applied.
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