參數(shù)資料
型號： ADSP-21369KSWZ-1A
廠商： Analog Devices Inc
文件頁數(shù)： 10/64頁
文件大小： 0K
描述： IC DSP 32BIT 266MHZ 208-LQFP
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點
接口： DAI，DPI
時鐘速率： 266MHz
非易失內(nèi)存： ROM（768 kB）
芯片上RAM： 256kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 208-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 208-LQFP-EP（28x28）
包裝： 托盤
配用： ADZS-21369-EZLITE-ND - KIT EVAL EZ LITE ADDS-21369
Rev. F
|
Page 18 of 64
|
October 2013
PACKAGE INFORMATION
The information presented in Figure 4 provides details about
the package branding for the ADSP-21367/ADSP-21368/
ADSP-21369 processors. For a complete listing of product avail-
ESD CAUTION
MAXIMUM POWER DISSIPATION
See the Engineer-to-Engineer Note “Estimating Power Dissipa-
tion for ADSP-21368 SHARC Processors” (EE-299) for detailed
thermal and power information regarding maximum power dis-
sipation. For information on package thermal specifications, see
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 10 may cause perma-
nent damage to the device. These are stress ratings only;
functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
TIMING SPECIFICATIONS
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
ence levels.
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Core Clock Requirements
The processor’s internal clock (a multiple of CLKIN) provides
the clock signal for timing internal memory, processor core, and
serial ports. During reset, program the ratio between the proces-
sor’s internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG1–0 pins.
The processor’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL,
see Figure 5). This PLL-based clocking minimizes the skew
between the system clock (CLKIN) signal and the processor’s
internal clock.
Voltage Controlled Oscillator
In application designs, the PLL multiplier value should be
selected in such a way that the VCO frequency never exceeds
fVCO specified in Table 13.
The product of CLKIN and PLLM must never exceed 1/2 of
fVCO (max) in Table 13 if the input divider is not enabled
(INDIV = 0).
Figure 4. Typical Package Brand
Table 9. Package Brand Information
Brand Key
Field Description
t
Temperature Range
pp
Package Type
Z
RoHS Compliant Option
cc
See Ordering Guide
vvvvvv.x
Assembly Lot Code
n.n
Silicon Revision
#
RoHS Compliant Designation
yyww
Date Code
vvvvvv.x n.n
tppZ-cc
S
ADSP-2136x
a
#yyww country_of_origin
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Table 10. Absolute Maximum Ratings
Parameter
Rating
Internal (Core) Supply Voltage (V
DDINT)–0.3 V to +1.5 V
Analog (PLL) Supply Voltage (A
VDD)–0.3 V to +1.5 V
External (I/O) Supply Voltage (V
DDEXT)–0.3 V to +4.6 V
Input Voltage
–0.5 V to +3.8 V
Output Voltage Swing
–0.5 V to V
DDEXT + 0.5 V
Load Capacitance
200 pF
Storage Temperature Range
–65
C to +150C
Junction Temperature Under Bias
125
C
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