2C Serial Real-Time Clock 13 of 20 Table 4. Alarm Mask Bits DY/ DT ALARM 1 REGISTER MASK BITS " />
參數(shù)資料
型號: DS1339U-3+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 5/20頁
文件大?。?/td> 0K
描述: IC RTC I2C W/ALARM 8-USOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 3,000
類型: 時鐘/日歷
特點: 警報器,閏年,方波輸出,涓流充電器
時間格式: HH:MM:SS(12/24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 3.3 V
電壓 - 電源,電池: 1.3 V ~ 3.7 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-uMAX
包裝: 帶卷 (TR)
DS1339 I
2C Serial Real-Time Clock
13 of 20
Table 4. Alarm Mask Bits
DY/
DT
ALARM 1 REGISTER MASK BITS
(Bit 7)
ALARM RATE
A1M4
A1M3
A1M2
A1M1
X
1
Alarm once per second
X
1
0
Alarm when seconds match
X
1
0
Alarm when minutes and seconds match
X
1
0
Alarm when hours, minutes, and seconds match
0
Alarm when date, hours, minutes, and seconds
match
1
0
Alarm when day, hours, minutes, and seconds match
DY/
DT
ALARM 2 REGISTER MASK BITS
(Bit 7)
ALARM RATE
A2M4
A2M3
A2M2
X
1
Alarm once per minute (00 sec. of every min.)
X
1
0
Alarm when minutes match
X
1
0
Alarm when hours and minutes match
0
Alarm when date, hours, and minutes match
1
0
Alarm when day, hours, and minutes match
SPECIAL-PURPOSE REGISTERS
The DS1339 has two additional registers (control and status) that control the RTC, alarms, and square-wave
output.
CONTROL REGISTER (0Eh)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
EOSC
0
BBSQI
RS2
RS1
INTCN
A2IE
A1IE
Bit 7: Enable Oscillator
(EOSC). This bit when set to logic 0 starts the oscillator. When this bit is set to a logic 1,
the oscillator is stopped. This bit is enabled (logic 0) when power is first applied.
Bit 5: Battery-Backed Square-Wave and Interrupt Enable (BBSQI). This bit when set to a logic 1 enables the
square wave or interrupt output when VCC is absent and the DS1339 is being powered by the VBACKUP pin. When
BBSQI is a logic 0, the SQW/
INT pin goes high impedance when V
CC falls below the power-fail trip point. This bit is
disabled (logic 0) when power is first applied.
Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the square-wave output when the
square wave has been enabled. Table 5 shows the square-wave frequencies that can be selected with the RS bits.
These bits are both set to logic 1 (32kHz) when power is first applied.
Table 5. SQW/
INT Output
INTCN
RS2
RS1
SQW/
INT
OUTPUT
A2IE
A1IE
0
1Hz
X
0
1
4.096kHz
X
0
1
0
8.192kHz
X
0
1
32.768kHz
X
1
X
A1F
0
1
X
A2F
1
0
1
X
A2F + A1F
1
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