2C Serial Real-Time Clock 16 of 20 Figure 5. Programmable Trickle Charger I 2" />
參數(shù)資料
型號: DS1339U-33+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 8/20頁
文件大?。?/td> 0K
描述: IC RTC I2C W/ALARM 8-USOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 3,000
類型: 時鐘/日歷
特點: 警報器,閏年,方波輸出,涓流充電器
時間格式: HH:MM:SS(12/24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.97 V ~ 5.5 V
電壓 - 電源,電池: 1.3 V ~ 3.7 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應商設備封裝: 8-uMAX
包裝: 帶卷 (TR)
DS1339 I
2C Serial Real-Time Clock
16 of 20
Figure 5. Programmable Trickle Charger
I
2C SERIAL DATA BUS
The DS1339 supports the I
2C bus protocol. A device that sends data onto the bus is defined as a transmitter and a
device receiving data as a receiver. The device that controls the message is called a master. The devices that are
controlled by the master are referred to as slaves. The bus must be controlled by a master device that generates
the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1339
operates as a slave on the I
2C bus. Within the bus specifications, a standard mode (100kHz cycle rate) and a fast
mode (400kHz cycle rate) are defined. The DS1339 works in both modes. Connections to the bus are made via the
open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (Figure 6):
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the
data line while the clock line is HIGH are interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
START data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH,
defines a START condition.
STOP data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is
HIGH, defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line is
stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during
the LOW period of the clock signal. There is one clock pulse per bit of data.
1 OF 16 SELECT
NOTE: ONLY 1010 ENABLES CHARGER
1 OF 2
SELECT
1 OF 3
SELECT
TCS3
TCS2
TCS1
TCS0
DS1
DS0
ROUT1
ROUT0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
250
2k
4k
R1
R3
R2
TRICKLE CHARGE REGISTER
TCS0-3
= TRICKLE CHARGER SELECT
DS0-1
= DIODE SELECT
ROUT0-1 = RESISTOR SELECT
VCC
VBACKUP
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