I2C RTC with Trickle Charger 4 Maxim Integrated DS1340 POWER-UP/POWER-DOWN CHARA" />
參數(shù)資料
型號(hào): DS1340Z-18+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 11/16頁(yè)
文件大?。?/td> 0K
描述: IC RTC I2C W/CHARGER 1.8V 8-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 100
類型: 時(shí)鐘/日歷
特點(diǎn): 閏年,方波輸出,涓流充電器
時(shí)間格式: HH:MM:SS(24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 1.71 V ~ 5.5 V
電壓 - 電源,電池: 1.3 V ~ 3.7 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
I2C RTC with Trickle Charger
4
Maxim Integrated
DS1340
POWER-UP/POWER-DOWN CHARACTERISTICS
(TA = -40°C to +85°C) (Figure 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Recovery at Power-Up
tREC
(Note 17)
2
ms
VCC Fall Time; VPF(MAX) to
VPF(MIN)
tVCCF
300
s
VCC Rise Time; VPF(MIN) to
VPF(MAX)
tVCCR
0s
WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup mode.
Note 1:
Limits at -40°C are guaranteed by design and not production tested.
Note 2:
All voltages are referenced to ground.
Note 3:
Measured at VCC = typ, VBACKUP = 0V, register 08h = A5h.
Note 4:
The use of the 250
Ω trickle-charge resistor is not allowed at VCC > 3.63V and should not be enabled.
Note 5:
Measured at VCC = typ, VBACKUP = 0V, register 08h = A6h.
Note 6:
Measured at VCC = typ, VBACKUP = 0V, register 08h = A7h.
Note 7:
ICCA—SCL clocking at max frequency = 400kHz.
Note 8:
Specified with I2C bus inactive.
Note 9:
Measured with a 32.768kHz crystal attached to the X1 and X2 pins.
Note 10:
Limits at +25°C are guaranteed by design and not production tested.
Note 11:
After this period, the first clock pulse is generated.
Note 12:
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIH(MIN) of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
Note 13:
The maximum tHD:DAT only has to be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 14:
A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT
≥ to 250ns must be met. This
is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the
low period of the SCL signal, it must output the next data bit to the SDA line tR MAX + tSU:DAT = 1000 + 250 = 1250ns
before the SCL line is released.
Note 15:
CB—total capacitance of one bus line in pF.
Note 16:
The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the 0V
≤ VCC
VCCMAX and 1.3V
≤ VBAT ≤3.7V range.
Note 17:
This delay applies only if the oscillator is enabled and running. If the oscillator is disabled or stopped, no power-up delay
occurs.
SCL
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
SDA
STOP
START
REPEATED
START
tBUF
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tHD:STA
tSP
tSU:STA
tHIGH
tR
tF
tLOW
Figure 1. Data Transfer on I2C Serial Bus
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