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參數(shù)資料
| 型號： | DS1344E-33+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC SPI 3.3V 20TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，閏年，NVRAM，方波輸出，涓流充電器 |
| 存儲容量： | 96B |
| 時(shí)間格式： | HH:MM:SS（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | SPI |
| 電源電壓： | 3 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
11
Maxim Integrated
Low-Current SPI/3-Wire RTCs
DS1343/DS1344
Register Map
Table 1 shows the devices’ register map. During a mul-
tibyte RTC access, if the address pointer reaches the
end of the register space (1Fh), it wraps around to loca-
tion 00h. During a multibyte RAM access, if the address
pointer reaches the end of the register space (7Fh), it
wraps around to location 20h. On either the rising edge
of CE or an RTC address pointer wrap around, the cur-
rent time is transferred to a secondary set of registers.
The time information is read from these secondary regis-
ters, while the clock continues to run. This eliminates the
need to reread the registers in case the main registers
update during a read.
Clock and Calendar (00h–06h)
The time and calendar information is obtained by reading
the appropriate register bytes. Table 1 shows the RTC
registers. The time and calendar are set or initialized by
writing the appropriate register bytes. The contents of
the time and calendar registers are in the BCD format.
The Day register increments at midnight and rolls over
from 7 to 1. Values that correspond to the day-of-week
are user defined, but must be sequential (i.e., if 1 equals
Sunday, then 2 equals Monday, and so on). Illogical time
and date entries result in undefined operation.
The devices can be run in either 12-hour or 24-hour
mode. Bit 6 of the Hours register is defined as the 12- or
24-hour mode-select bit. When high, the 12-hour mode
is selected. In the 12-hour mode, bit 5 is the AM/PM bit,
with a content of 1 being PM. In the 24-hour mode, bit 5
is the 20-hour field. Changing the 12/24 mode-select bit
requires that the Hours data subsequently be reentered,
including the Alarm register (if used). The Century bit (bit
7 of Month) is toggled when the Years register rolls over
from 99 to 00. On a power-on reset (POR), the time and
date are set to 00:00:00 01/01/00 (hh:mm:ss DD/MM/YY),
and the Day register is set to 01.
Alarms (07h–0Eh)
The devices contains two time-of-day/date alarms. Alarm
0 can be set by writing to registers 07h–0Ah. Alarm 1 can
be set by writing to registers 0Bh–0Eh. The alarms can
be programmed to activate the INT0 or INT1 outputs on
an alarm match condition (see Table 2). Bit 7 of each
of the time of day/date alarm registers are mask bits.
When all the mask bits for each alarm are 0, an alarm
only occurs when the values in the timekeeping registers
00h–06h match the values stored in the alarm registers.
The alarms can also be programmed to repeat every
second, minute, hour, or day. Configurations not listed
in the table result in illogical operation. POR values are
undefined.
When the RTC register values match alarm register
settings, the corresponding alarm flag bit (IRQF0 or
IRQF1) is set to 1 in the Status register. If the corre-
sponding alarm interrupt enable bit (A0IE or A1IE) is
also set to 1 in the Control register, the alarm condition
activates the output(s) defined by the INTCN bit. Upon
an active alarm, clearing the associated IRQF[1:0] bit
deasserts the selected interrupt output while leaving
the alarm enabled for the next occurrence of a match.
Alternatively, clearing the A_IE bit deasserts the output
and inhibits further output activations.
The alarm flags are always active, fully independent of
the A_IE bit states. All alarm registers should be written
to logic zero to disable the alarm matching.
Figure 1. Layout Example
LOCAL GROUND PLANE (LAYER 2)
CRYSTAL
GND
X2
X1
NOTE: AVOID ROUTING SIGNAL LINES
IN THE CROSSHATCHED AREA
(UPPER LEFT QUADRANT) OF
THE PACKAGE UNLESS THERE IS
A GROUND PLANE BETWEEN THE
SIGNAL LINE AND THE DEVICE PACKAGE.
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