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參數(shù)資料
| 型號(hào)： | DS1371U+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BINARY COUNTER 32-BIT 8-USOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類型： | 二進(jìn)制計(jì)數(shù)器 |
| 特點(diǎn)： | 警報(bào)器，方波輸出，監(jiān)視計(jì)時(shí)器 |
| 時(shí)間格式： | 二進(jìn)制 |
| 數(shù)據(jù)格式： | 二進(jìn)制 |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 1.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
DS1371
12 of 15
Data valid: The state of the data line represents valid data when, after a START condition, the
data line is stable for the duration of the high period of the clock signal. The data on the line must
be changed during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition.
The number of data bytes transferred between the START and the STOP conditions is not limited,
and is determined by the master device. The information is transferred byte-wise and each
receiver acknowledges with a ninth bit. Within the I2C bus specifications a standard mode
(100kHz clock rate) and a fast mode (400kHz clock rate) are defined.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge
after the reception of each byte. The master device must generate an extra clock pulse, which is
associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in
such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related
clock pulse. Setup and hold times must be taken into account. A master must signal an end of data
to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the
slave. In this case, the slave must leave the data line HIGH to enable the master to generate the
STOP condition.
Figure 4. I
2C Data Transfer Overview
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| DS1372 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:I2C, 32-Bit, Binary Counter Clock with 64-Bit ID |
| DS1372U+ | 功能描述:實(shí)時(shí)時(shí)鐘 I2C 32 bit Binary Counter w/64 Bit ID RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1372U+T&R | 制造商:Maxim Integrated Products 功能描述:RTC W/SERIAL NUMBER - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC BINARY COUNTER 32-BIT 8-USOP |
| DS1372U+T&R | 功能描述:實(shí)時(shí)時(shí)鐘 I2C 32 bit Binary Counter w/64 Bit ID RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1374 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output |
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