參數(shù)資料
型號(hào): DS1374U-3+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 4/18頁(yè)
文件大?。?/td> 0K
描述: IC RTC I2C W/CHARGER 10-USOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 50
類型: 二進(jìn)制計(jì)數(shù)器
特點(diǎn): 警報(bào)器,方波輸出,涓流充電器,監(jiān)視計(jì)時(shí)器
時(shí)間格式: 二進(jìn)制
數(shù)據(jù)格式: 二進(jìn)制
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 3.3 V
電壓 - 電源,電池: 1.3 V ~ 3.7 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-µMAX
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1434 (CN2011-ZH PDF)
Special Purpose Registers
The DS1374 has two additional registers (07h–08h) that
control the WD/ALM counter and the square-wave, inter-
rupt, and reset outputs.
Control Register (07h)
Bit 7/Enable Oscillator (EOSC). When set to logic 0,
the oscillator is started. When set to logic 1, the oscilla-
tor is stopped. When this bit is set to logic 1, the oscilla-
tor is stopped and the DS1374 is placed into a
low-power standby mode (IDDR). This bit is clear (logic
0) when power is first applied. When the DS1374 is
powered by VCC, the oscillator is always on regardless
of the state of the EOSC bit.
Bit 6/WD/A
AL
LM
M Counter Enable (WACE). When set to
logic 1, the WD/ALM counter is enabled. When set to
logic 0, the WD/ALM counter is disabled, and the 24
bits can be used as NV RAM. This bit is clear (logic 0)
when power is first applied.
Bit 5/WD/A
AL
LM
M Counter Select (WD/ALM). When set to
logic 0, the counter decrements every second until it
reaches zero and is then reloaded and restarted. When
set to logic 1, the WD/ALM counter decrements every
1/4096 of a second (approximately every 244s) until it
reaches zero, sets the AF bit in the status register, and
stops. If any of the WD/ALM counter registers are
accessed before the counter reaches zero, the counter
is reloaded and restarted. This bit is clear (logic 0)
when power is first applied.
Bit 4/Battery-Backed Square-Wave Enable (BBSQW).
This bit, when set to logic 1, enables the square-wave
output when VCC is absent and when the DS1374 is
being powered by the VBACKUP pin. When BBSQW is
logic 0, the SQW pin goes high impedance when VCC
falls below the power-fail trip point. This bit is disabled
(logic 0) when power is first applied.
Bit 3/Watchdog Reset Steering Bit (WDSTR). This bit
selects which output pin the watchdog-reset signal
occurs on. When the WDSTR bit is set to logic 0, a
250ms pulse occurs on the RST pin if WD/ALM = 1 and
the WD/ALM counter reaches zero. The 250ms reset
pulse occurs on the INT pin when the WDSTR bit is set
to logic 1. This bit is logic 0 when power is first applied.
Bits 2, 1/Rate Select (RS2 and RS1). These bits con-
trol the frequency of the square-wave output when the
square wave has been enabled. Table 4 shows the
square-wave frequencies that can be selected with the
RS bits. These bits are both set (logic 1) when power is
first applied.
Bit 0/Alarm Interrupt Enable (AIE). When set to logic
1, this bit permits the alarm flag (AF) bit in the status
register to assert INT (when WDSTR = 1). When set to
logic 0 or WDSTR is set to logic 0, the AF bit does not
initiate the INT signal. If the WD/ALM bit is set to logic 1
and the AF flag is set, writing AIE to zero does not trun-
cate the 250ms pulse on the INT pin. The AIE bit is at
logic 0 when power is first applied. The INT output is
available while the device is powered by either supply.
RS2
RS1
SQUARE-WAVE OUTPUT FREQUENCY
0
1Hz
0
1
4.096kHz
1
0
8.192kHz
1
32.768kHz
Table 4. Square-Wave Output Frequency
DS1374
I2C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
12
____________________________________________________________________
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EOSC
WACE
WD/ALM
BBSQW
WDSTR
RS2
RS1
AIE
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